verilog XADC output for module instantiation

[Shruthi]

Hello all,

 

I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. 

 

Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter.

 

`timescale 1ns/1ps

module ug480_tb;
reg [3:0] VAUXP, VAUXN;
reg VP, VN;
reg RESET;
reg DCLK;

wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX;
wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX6, MEASURED_AUX7;
wire [15:0] MEASURED_AUX14, MEASURED_AUX15;
wire [7:0] ALM;
wire OT;
wire EOC;
wire EOS;
wire [4:0] CHANNEL;

initial
begin
DCLK = 0;
RESET = 0;
end

always #(10) DCLK= ~DCLK;

// Instantiate the Unit Under Test (UUT)
ug480 uut (
.VAUXP (VAUXP),
.VAUXN (VAUXN),
.RESET (RESET),
.ALM (ALM),
.DCLK (DCLK),

.MEASURED_TEMP (MEASURED_TEMP),
.MEASURED_VCCINT (MEASURED_VCCINT),
.MEASURED_VCCAUX (MEASURED_VCCAUX),
.MEASURED_VCCBRAM (MEASURED_VCCBRAM),
.MEASURED_AUX6 (MEASURED_AUX6),
.MEASURED_AUX7 (MEASURED_AUX7),
.MEASURED_AUX14 (MEASURED_AUX14),
.MEASURED_AUX15 (MEASURED_AUX15)
);

integer i [0:4];

wire [15:0] e [0:3]
reg [15:0] x [0:3];
initial begin
for (i=0; i<4; i=i+1)
begin
x = MEASURED_AUX6;
end
end

 

CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3]));
endmodule

 

Thank you,

Shruthi Sampathkumar.

[JColvin]

Hi Shruthi,

I'm not the most experienced with Verilog so I can't guarantee this will be the most complete answer (or have correct syntax) but if you are wanting to store results to separate input parameters, you would need to do so in the for loop. Right now, it looks like you are just re-assigning x the MEASURED_AUX6 value four different times. It would probably be easier to store values in an array so you had x[ i ] = MEASURED_AUX6, so you have four stored values in the array called x. 

However, I don't know how to set up the rest pieces so that the array is initialized appropriately and to make sure that each x value gets a different part of the MEASURED_AUX6 parameter rather than having all four x's get the exact same value simultaneously. For that, I'll ask some of our applications engineers about (and to have them correct what I've said if necessary).

Thanks,
JColvin

[TommyK]

Hi Shruthi,

I think you'll want to make a small state machine to accomplish this. 

reg [2:0] state=0'b000;

always@(posedge(clk)) begin

switch(state):

    case 0: begin

                 do stuff

                 state<=1

   case 1: begin

                (and so forth)

                 etc...

endcase

end