Xilinx ZCU104 and Pmod I2S2

[libswig]

Hi,
I was recommended Pmod audio adapter as a solution for audio capture with Xilinx ZCU104 because this board does not have audio connectors of its own. There is an I2S2 product guide for audio receiver / transmitter provided by Xilinx, but describes it only in general terms. Diligent, on the other hand, covers only its own boards in combination with the audio adapter. I need some fool proof guidance on the issue. Can you help, please?

Thanks,  Libor

[jpeyron]

Hi @libswig,

Welcome to the Digilent forums!

Here is a forum thread that is has the same issue with a different Pmod. The solution is the same.

best regards,

Jon

[libswig]

Hi Jon,

My appreciation for your prompt reply. Actually I noted this post but I must admit I was unable to apply it because I was not sure about proposed actions and some abbreviations. Please clarify or be more specific about the steps.

This is what I did:

Download Pmod-I2S2 Volume Control Demo from link on https://reference.digilentinc.com/reference/pmod/pmodi2s2/start

Vivado, Open a project,

readme file states:

This project is only supported in the 2017.4 version of Vivado

- am I safe with Vivado 2018.3 ?

Available boards are:

Arty A7-35, Arty A7-100, Arty S7-25, Arty S7-50,Cora Z7-07S,Cora Z7-10,Cmod S7-25

Does it matter which one to select?

Vivado, Create project, RTL Project,

I get empty project for Artix-7 product family

I follow readme, TCL console, CD into arty-a7-35, "source ./create_project.tcl"

     -    ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

Is this message to be expected?

How to execute next step "add the IP to a BD, then edit in IP packager" instruction?

 

As you can see, this is a bumpy ride and I am afraid I would be thrown in the ditch

Thanks for help, Libor

 

[jpeyron]

Hi @libswig,

Looking further into this project there is no IP Core for the Pmod I2S2. The Pmod I2S2 is being used through Verilog. 

You should create a new project selecting the ZCU104. You should be able to use the Verilog without changing anything in Vivado 2018.3.  You will need to use the attached XDC file as a reference for the ZCU104's XDC.

best regards,

Jon 

axis_volume_controller.v top.v axis_i2s2.v Cora-Z7-10-Master.xdc

[libswig]

Hi Jon,

You've come a long way to help me, but I am afraid you have to treat me like a total dummy ?.

Let me share my progress:

Vivado,

Add Sources, axis_i2s2.v, axis_volume_controller.v, top.v

Add Constraints, Cora-Z7-10-Master.xdc

Default Part, Boards, ZCU104

In Project Manager, Design sources, m_clk item is decorated by question mark icon - how to treat it?

Clocking Wizard pictures, why and how?

As you can see, I need step-by-step coaching, if you are willing to help further, I will be happy.

Libor

[jpeyron]

Hi @libswig,

Instead of adding the Cora Z7 XDC you should add the XDC file for the ZCU104 found here. I attached a screen shot showing that you will  need to expand the associated files to be able to select the xdc for the ZCU104. You should use the Cora Z7 XDC as a reference of what pins will need to be uncommented and how to set up the  ZCU104 xdc.

I believe you will need to add the clocking wizard  from the IP catalog under the flow  navigator. Use the settings from the attached screen shots above.

best regards,

Jon

[libswig]

Hi Jon,

I have set up the vivado project as instructed, included constraints zcu104 XDC file. however, I receive 'set_property expects at least one object' for each port I use, running synthesis. See example for G8 pin:

set_property PACKAGE_PIN G8       [get_ports "PMOD0_0"] ;

set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD0_0"] ;

set_property -dict { PACKAGE_PIN G8   IOSTANDARD LVCMOS33 } [get_ports { tx_mclk }];

Thank you for your help, Libor

zcu104_Rev1.0_U1_01302018.xdc

[jpeyron]

Hi @libswig,

Please attach your wrapper file from Vivado.

best regards,

Jon

[libswig]

Hi,

My design sources structure is as follows:

top.v

- m_clk : clkwiz_0

- m_i2s2 : axis_i2s2

- m_vc : axis_volume_controllertop.v

Clock uses differential clock source represented by clk_n and clk_p wires.

Synth message (30x, for all ports): [Vivado 12-584] No ports matched 'CLK_300_N'. ["C:/Users/h326709/Downloads/zcu104_Rev1.0_U1_01302018.xdc":589]

Best Regards, Libor

axis_i2s2.v axis_volume_controller.v

[jpeyron]

Hi @libswig,

I believe you should comment out this clock in the XDC

set_property PACKAGE_PIN AH17     [get_ports "CLK_300_N"] ;# Bank  64 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_64
set_property IOSTANDARD  DIFF_SSTL12 [get_ports "CLK_300_N"] ;# Bank  64 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_64
set_property PACKAGE_PIN AH18     [get_ports "CLK_300_P"] ;# Bank  64 VCCO - VCC1V2   - IO_L13P_T2L_N0_GC_QBC_64
set_property IOSTANDARD  DIFF_SSTL12 [get_ports "CLK_300_P"] ;# Bank  64 VCCO - VCC1V2   - IO_L13P_T2L_N0_GC_QBC_64

since you are using the PL Clock.

Also looking at the top.v and the XDC file there are output wires that need to be constrained to pins in the XDC.

    output wire tx_mclk,
    output wire tx_lrck,
    output wire tx_sclk,
    output wire tx_data,
    output wire rx_mclk,
    output wire rx_lrck,
    output wire rx_sclk,
    input  wire rx_data

 

In the XDC for the Cora Z7 the constraints for these are

# Pmod Header JA
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { tx_mclk }]; #IO_L17P_T2_34 Sch=ja_p[1]
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { tx_lrck }]; #IO_L17N_T2_34 Sch=ja_n[1]
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { tx_sclk }]; #IO_L7P_T1_34 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { tx_data }]; #IO_L7N_T1_34 Sch=ja_n[2]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { rx_mclk }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { rx_lrck }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { rx_sclk }]; #IO_L22P_T3_34 Sch=ja_p[4]
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { rx_data }]; #IO_L22N_T3_34 Sch=ja_n[4]

 

So your XDC for the Pmod port should look something like below:

set_property PACKAGE_PIN G8       [get_ports "tx_mclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L12N_AD0N_87
set_property IOSTANDARD  LVCMOS33 [get_ports "tx_mclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L12N_AD0N_87
set_property PACKAGE_PIN H8       [get_ports "tx_lrck"] ;# Bank  87 VCCO - VCC3V3   - IO_L12P_AD0P_87
set_property IOSTANDARD  LVCMOS33 [get_ports "tx_lrck"] ;# Bank  87 VCCO - VCC3V3   - IO_L12P_AD0P_87
set_property PACKAGE_PIN G7       [get_ports "tx_sclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L11N_AD1N_87
set_property IOSTANDARD  LVCMOS33 [get_ports "tx_sclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L11N_AD1N_87
set_property PACKAGE_PIN H7       [get_ports " tx_data"] ;# Bank  87 VCCO - VCC3V3   - IO_L11P_AD1P_87
set_property IOSTANDARD  LVCMOS33 [get_ports " tx_data"] ;# Bank  87 VCCO - VCC3V3   - IO_L11P_AD1P_87
set_property PACKAGE_PIN G6       [get_ports " rx_mclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L10N_AD2N_87
set_property IOSTANDARD  LVCMOS33 [get_ports " rx_mclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L10N_AD2N_87
set_property PACKAGE_PIN H6       [get_ports " rx_lrck"] ;# Bank  87 VCCO - VCC3V3   - IO_L10P_AD2P_87
set_property IOSTANDARD  LVCMOS33 [get_ports " rx_lrck"] ;# Bank  87 VCCO - VCC3V3   - IO_L10P_AD2P_87
set_property PACKAGE_PIN J6       [get_ports " rx_sclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L9N_AD3N_87
set_property IOSTANDARD  LVCMOS33 [get_ports " rx_sclk"] ;# Bank  87 VCCO - VCC3V3   - IO_L9N_AD3N_87
set_property PACKAGE_PIN J7       [get_ports "rx_data "] ;# Bank  87 VCCO - VCC3V3   - IO_L9P_AD3P_87
set_property IOSTANDARD  LVCMOS33 [get_ports "rx_data "] ;# Bank  87 VCCO - VCC3V3   - IO_L9P_AD3P_87

It looks like most of your issues are coming from discrepancies between the top and xdc files. Also make sure the out put clock in the clocking wizard is 22.591 MHz as shown in the attached screen shot above.

best regards,

Jon

 

 

 

  

[libswig]

Hi,

Almost there - except the sound. 

I have done all down to programming the device. However the sweet output sound still evades me. I suspect many things can go wrong. Can you suggest how to debug the solution? I have used leds to indicate clock and rx data handling. I also hope that attached schematics can help you spot the issue.  I attach v files as well.

Please note that I disabled multiplier in volume controller to make sure I run at "full throttle".

Thank you for the guidance. Libor

top.v axis_i2s2.v axis_volume_controller.v zcu104_Rev1.0_U1_01302018.xdc

[jpeyron]

Hi @libswig,

I'm not seeing anything directly wrong with your xdc or verilog files. Please attach a screen shot of the output tab on the clocking wizard. 

best regards,

Jon