The clk is 100MHZ, its period is 10ns. So the clk_0's period is 1s, and the clk_0's period is 4s. Then I connected clk_0 and clk_1 to two led lights to observe the result. Clk_0 is correct, but clk_1 is wrong.

However, I simply modified the code to look like this:

The problem disappears. The difference between the two codes is whether the clkout signal uses combinatorial logic or sequential logic. I don't know what effect this will have. Can someone tell me?

## Question

## Shaw 0

Hello, there

I have written a frequency divider.sv with SystemVerilog. But I have a problem about it.

I use the following code to instantiate a two-level divider:

`divider CLK_DIV_1 ( .clk (clk), .rst (rst), .n (32'd100000000), .clkout (clk_0) ); divider CLK_DIV_2 ( .clk (clk_0), .rst (rst), .n (32'd4), .clkout (clk_1) );`

The

clkis 100MHZ, its period is 10ns. So theclk_0's period is 1s, and theclk_0's period is 4s. Then I connected clk_0 and clk_1 to two led lights to observe the result. Clk_0 is correct, but clk_1 is wrong.However, I simply modified the code to look like this:

``timescale 1ns / 1ps module divider ( input logic rst, input logic clk, input logic [31:0] n, output logic clkout ); logic[31:0] q; always_ff @(posedge clk, posedge rst) begin if (rst) q <= 0; else if (q >= n - 1) q <= 0; else q <= q + 1'b1; clkout <= (q < (n>>1)); end // assign clkout = (q < (n>>1)); endmodule`

The problem disappears. The difference between the two codes is whether the clkout signal uses combinatorial logic or sequential logic. I don't know what effect this will have. Can someone tell me?

PS: I am using Vivado 2018.2 and Nexys4DDR.

Thanks.

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