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m72

Logic Detector as trigger in Scope. Is it possible?

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Hello!

Can be "Logic Detector" added to trigger menu in "Scope" instrument?
I use this workaround in WaveForms V3.11.7 (beta, Windows, 64 bit):
1. In AD2 settings set "Trigger 1" to "Logic Detector"
2. In "Scope" use "Trigger 1" as trigger.

With best regards, Mikhail.

1.png

2.png

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Hi @m72

It will be added to the next software.
Thank you for the observation.

In case you need it, you can also use the Scope in mixed mode, having Digital/Logic Analyzer channels in the same interface:

image.png.122eb0e938324cc427e1c3453b6e3365.png

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Hello!

In pattern generator.
When I set "Duty" for "Clock" signal to small value like 0.01% ... 0.1% preview turns to noise. Also happen with "Pulse".
But the signal is good like described by settings.

With best regards, Mikhail.
 

23.png

31.png

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Hi @m72

The preview will represent such corner cases correctly in the next software release.

Thank you for the observation.

image.png.b6f3d825bfd1d9c7b56e9c2e718ad70a.png

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Hi @m72

Thank you for the observation.

I have fixed this display glitch with large amount of samples and constant SPI data, for the next software release.

PS: You can use the Events view to pinpoint words/bytes/events and double-click in this list will navigate the waveform (change time position) to be visible.

image.png.a45d73c83d3a6946430adbeab1bc7597.png

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Posted (edited)

Hello!

Proposition. Please add different subaddresses for Write and Read. 
Or remain subaddress only for reading because subaddress make sense only for it.

With best regards, Mikhail.

 

18.png

Edited by m72

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I2C decoding. Theoretically, this decoding example is correct, this is a “STOP event”. But almost everything works fine, for the I2C slave, these fronts are simultaneously. Maybe add settings for the "gap" or something else?

16.png

17.png

LCD_I2C_error.dwf3work

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Hi @m72

In this high resolution capture it looks like SDA is rising while SCL is still high.
To overcome such situations lower the sample Rate, to 100MHz or lower. 
This way it will likely capture SDA and SCL change at the same time, which should be interpreted correctly.

Note that the setup time for Stop condition is no respected:

image.thumb.png.2bdae9a4baaa9528a6ba3e79416e8812.png

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Posted (edited)

Hello!

This is my point of view for I2C decoder. 
1. START-STOP without any data transfer is allowed, not an error.
2. SDA changing on SCL falling usually work but sometimes  need a detection.
3. SDA changing on SCL rising not allowed in standard but can work.

This custom script can be configured:
a. View all byte or "bit by bit". If an error during byte decoding is detected view changes to "bit by bit" till next byte.
b. Detections of 1, 2, 3 have own settings.
c. Jitter detector width.

With best regards, Mikhail.
P.S.
I2C_decoder a few times updated. I think now it is well optimized but still simple.
Why did I write this script? I work with an LCD controller (RW1087) through I2C. In static mode, you need to write one byte for each segment of the LCD. So, 128 segments -> 128 bytes, this takes too much time. So I skipped some recommendations. For example, “change SDA only after changing SCL”, I write one value to the microcontroller port for both. But because of the jitter between the SCL and the SDA, the I2C decoder built into the WavesForms cannot decode the signal properly.

31.png

 

 

23.png

 

 

 

 

 

 

 

 

I2C_decoder4.dwf3work

Edited by m72
new decoder version

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Hello!

WaveForms, 3.11.17, Windows 64 + Digital Discovery.

Mismatch of DIN pins and input modes at 800 MHz sampling rate.

With best regards, Mikhail.

28.png

29.png

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Hi @m72

Thank you for the observation and sorry for this.
It is fixed in the latest version:
https://forum.digilentinc.com/topic/8908-waveforms-beta-download/

I just notice that certain frequencies cause PLL not locked error.
In this case select "Force Programming".
I have to look exactly what synthesizer settings or PLL reset sequences lead to such problems.

image.png.098a023147e9fabddb10cc2655d1b101.png

 

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Posted (edited)

Hello!

Digital Discovery, WaveForms 3.11.19, Windows 7, x64.

I have an "pit-stop" when change time scale with roll of my mouse.
In ms/div
20->10->5 ...stop... 5->10->20->10->5 ...stop...
Ok. With shift. 5->4.165 Without shift. 4.165->2->5->10->5 ...stop....
Or may work if change fast from 10->2.
Also I found "pit stop" at 50Ms/div.

With best regards, Mikhail.
P.S.
Sometimes WF with DD in "recording" mode crashes on big source data like 256 Msamples. (Overclocked to 125 MHz -> 1G samples/s???)
P.P.S.
Does WF with DD always use internal RAM? Sometimes on "recording" of 50/100 M samples @10-100 MHz WF writes "Decrease sample rate, some samples can be ommited".

35.png

Edited by m72

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Hi @m72

I have fixed the "pit top" for next version.

I was unable to reproduce the crash. If you add multiple interpreters (Bus,I2C,SPI,UART...) it will use more memory and process the capture slower...

The DD ram is 4Gbit (256MB). 
With 8 bit sampling (input: 800MHz x8) you can capture in ram 256M samples, with 16 bit (400MHz x16) 128M, with 32 bit (100-200MHz x32) 64M (67108864).
At lower rate you can capture up to 100Mi samples. In this case the data is streamed over USB, which could lead to sample lost due to congestion.
 

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Hello!

An issue on opening project with two AD2 devices on one computer. Not a big deal.

Create project with AD2[1], configuration #4 (logic 16x16k). Save project.

A. If open this project with AD2[1], configuration #1
    "Project was created with AD2[1] configuration #4. Switch to configuration #4?" -> Yes - > AD2[1] configuration #4.
B. If open this project with AD2[2], configuration #1
    "Project was created with AD2[1] configuration #4. Switch to this device?" -> No -> AD2[2] configuration #1.
C. If open this project in first instance of WF with AD2[1] and try to open in second instance of WF with AD2[2].
    "Project was created with AD2[1] configuration #4. Switch to this device?" -> Yes -> "The device is being used by another application. Device programming failed". -> Ok.
    Side effect: DIO0 -> DIO16, DIO1 -> DIO17 and so on. DIO16 does not exist on AD2. :-)

On closing WF saves list of recent files only from last instance. Also not a big deal.

1. Open first WF and create project "A".
2. Open second WF and create project "B".
3. Exit second WF.
4. Exit first WF.

Reopen WF and in recent files there is only one project "A".
Workaround: open WF, open project "A", open project "B", exit WF. Now recent files list contains "A" & "B". It is good for a next month.

With best regards, Mikhail.

Edited by m72

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Pattern "Pulse". Is it right?
I need an 30 us impulse after 120 us delay.
DIO0 & DIO1 seems to work right, but I need to set "Counter Init" to 1.
I think it works next way:
1. Delay 120 us.
2. Start with zero
3. 1 tick with zero.
4. Pulse 1.
DIO2 & DIO3 are strange. 

 

38.png

EMU_2CH_EACH_V10.dwf3work

Edited by m72

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Hi @m72

The pulse preview is not correct. I will look into this.
Thank you for the observations.

You could use a custom bus or signals to easily create/modify such patterns.

image.png.c44edeec0a3331a2a7847cc904b9c3b1.png

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Thank you!
This is an signal emulator for an ultrasound metering system. So I need the best possible delay resolution (10 ns). The "pulse" has it in "simple form" and I can change it precisely for each channel.
The bus delay is also good. I just tried it. 
 

Edited by m72

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Ok. But problem with pulses that start at "High" is present. Line goes High on start ignoring delay settings. And falling down at expected time.

P.S.

May be it is better to fill delay before pulse with "Idle" value?

38.png

EMU_2CH_EACH_V10.dwf3work

Edited by m72

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Hello!

The initial clock signal level depends on the frequency and phase.
With phase == 0 - it works well. With phase = 180 degrees - so-so. (This signal is like a preview).

As far as I understand, these are rounding issues. But you must admit that it looks strange: I change the frequency slider - the initial signal level changes.

The delay parameter for signals is very useful. But in the general case, it would be nice to set the line state separately. It may have to separately process for each type of signal and even its value. I will try to systematize my experience a bit later.

Hmm... The negative delay time is actually "counter init = period - abs(delay)". I think this would be useful for a "custom" signal. Then you can start  the signal from the defined "half-bit."

It takes some time to think.

Best regards, Mikhail.
 

 

34.png

delay_error.dwf3work

Edited by m72

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Hi @m72

The 1kHz is generated from the 100MHz system clock with 50% duty.
The 1.1kHz is actually generated as 1.099989kHz with 49.9945% duty. Due to this the 180* phase, the middle falls in low level which gets used as initial value.
For the next release I have modified the duty to round up, so the 1.1kHz will have 50.005499945% duty and the 180* phase will start high.

I'm also adding negative delay for the next version.

Thank you for the observation.

Current version:
image.thumb.png.c1b05c22b6534b66c837620bfe8c7953.png

 

Next version:
image.thumb.png.02dcd89b5386d9731dffe538f08fe221.png

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