Bit error rate (BER) calculations

[Ahmed Alfadhel]

Hi,

I used Vivado IDE to design a transmitter and a receiver. In case I implemented my the transmitter on FPGA board and the receiver on  another FPGA board (ARTY 7), how to calculate BER value for this transceiver?

Thanks.

[D@n]

@Ahmed Alfadhel,

I like to use a basic LFSR when doing a BER test.  The LFSR can be used to generate a pseudorandom bit-sequence in the transmitter.  In the receiver, assuming you've used an LFSR, then there exists a linear combination of the input bits that will annihilate the sequence (turn all the bits to zero).  You can then measure BER based upon the number of bits that are zero at the output.  The biggest catch is that, depending upon the number of input bits required to generate the annihilator, you may end up with an estimate that's 3x larger than it needs to be (assuming a three tap annihilator).  A little bit of scaling on the back end will then return this to the BER measurement you are looking for.  The exception is that in really low BER environments, this method becomes too optimistic due to the math at the back end.

This article should tell you what you need to build an LFSR.  You'll probably want an LFSR with a longer period, though (google "maximal length LFSR"), and one that can be annihilated easily (google "feedthrough randomizer").  I know Sklar's Digital Communications has a table of polynomials you can use, as does Schneiers Applied Cryptography.  You are also likely to find similar tables on line if you google for them.

Dan