Regarding the capabilities of the Digital Discovery

[attila]

We got the following question:

Hello,

I'm interested in the Digital Discovery logic analyzer to capture the data on a parallel 12-bit clocked bus running at 4MHz.

I have the following three questions:

1. Can this device be operated through Python? I would like to set it up, trigger an acquisition and get the results back into python, all this in a loop that would allow multiple automated acquisitions. 

2. Can this device work in a mode where I can provide the clock line to a dedicated pin and then the 12-bit bus is sampled on the falling/rising edge? (Instead of oversampling at e.g. 20Mspls/s to retrieve all the waveforms)

3. Can this device decode the 12-bit parallel bus so I get back a word instead of separate bits?

Thanks for your help,

[attila]

The Digital Discovery lets you capture 8 lines at up to 800MHz or 16 at 400MHz or 32 at 200MHz, in 16 it fits 7+1
To capture 125MHz DDR signal you need sampling rate higher than 250MHz, like 400MHz

[TheoR]

Hi,

Thank you for you reply.

I didn't see the export function before you show me.

For Sync, I will try with the function include in "DigitalIn_Sync.py".

I've some problem to visualize result in your exemples script python.

I can't install on my computer this package "import matplotlib.pyplot as plt".

So in this file "DigitalIn_Acquisition.py", I use this way:

########################################################

f = open("record.csv", "w")
for v in rgwSamples:
i += 1
f.write("%d %s\n" % (v))
f.close()
#plt.plot(numpy.fromiter(rgwSamples, dtype = numpy.uint16))
#plt.show()

#########################################################

I wait an increment from zero to n of rgwSamples but the result didn't corresponding.

My data record are:

Num data
1 183
2 41
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0

......

 

 

Can you explain me what is happen?

[HoWei]

Okay thanks for clarification - in other words:

SDK does not provide the "high-level-function" of bus definition, as waveform-GUI does.

Interpretation of data has to be done by the user.

 

[attila]

Hi @HoWei

The SDK Digital-In functions provide raw data samples on 8, 16 or 32 bits, like a simple bus with DIN 0-7 or DIN 0-15 ...

[HoWei]

Okay, I will try to ask  more clearly.

In the Waveforms GUI a bus can be set up to analyze and interpret captured bus data and export it.

But I am using SDK to control the DigiDisco via python.

Is this bus-setup available via SDK, or do I have to create such a bus definition from scratch when using SDK ?

 

As far as I see from the given SDK examples, the capturing of DIN always applies to the whole DIN-Port (DIN0..23, DIO24..39) at once, and the data interpretatoin has to be done by the user-application. Is that true ?

 

 

 

 

[attila]

Hi @TheoR

I'm not sure if understand you question correctly...

You can export and import data to/from file in Logic Analyzer (File/Export see Source options and File/Import) and Pattern Generator custom signal/bus.

Regarding Sync mode in Python see the following posts:

[HoWei]

I am working myself thru the existing SDK python-examples - especially DigitalIn_Sync.py

Is the "either-edge" option already available thru WaveformSDK in the beta-version  ?

Can I set it by using:

# in sync mode the trigger is used for sampling condition
# trigger detector mask:          low &     hight & ( rising | falling )
dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(1), c_int(1))

Was the either edge function added to the trigger or to the bus-decoding ?

If for bus-decoding - how would I apply it via SDK - is this possible ?

 

[attila]

Hi @HoWei

The Sync mode has 90/100MHz limit, in other words 100M samples/second or 50MHz DDR upper limit. 
For 125MHz DDR signal use the previously mentioned method:

 

[TheoR]

Hi,

I've same problem. I need to sync.

Do you have an issue?

And I have another question: If we record a test file with patterns generator in Waveform, is it possible to load it directly in Python?

Thank you for your response.

 

 

 

 

[HoWei]

I received the Digi-Disco today and started evaluation.

I found the following mode, which is ( I think) what I will need:

- Sync-Trigger-Mode (allows 90MHz sampling rate on DIN0..23, DIO24..31)

- Bus with "either" - edge sampling

Apparently this setting starts when the first edge is detected and samples for a given number of samples (up to 100MSamples).

1. Do you see any issues with this settings ?

2. Is it possible to use "sync" trigge rmode with higher sampling rate ?

3. Is the "either-edge" option already available thru WaveformSDK in the beta-version - would like to programm in python ?

 

 

 

 

 

 

 

 

[attila]

Hi @HoWei

You can find the installer with the earlier mentioned changes here:
https://forum.digilentinc.com/topic/8908-waveforms-beta-download/

[HoWei]

Okay got it. As I have 9 DDR lines (8 data + 1 clock) the maximum sample rate is 400MHz in best case.

There are 7 lines left  - at least one more line I need to capture the Frame-Clock output of the ADC.

Thus only 6 lines are left for additional capturing with 400MHz.

Thanx - looking forward to the Beta-Version.

 

[HoWei]

No I lost you.

8 DDR Datalines + 1 DDR clockline (100MHz) - Why would I need to capture 16 signals ?

I would expect to capture 8 signals only with 100MHz (if 4x  oversampling is required to detect the edges capture - I agree to 400MHz sampling clock of the DigDisco).

Did you say 400MHz due to oversampling for proper edge-detection ?

Where do the 16 signal come from ?

 

[attila]

To interface with and ADC or DAC I would use an FPGA development board with DDRAM with suitable connector or shorter interface/wiring to the ADC/DAC board. This requires some experience in HDL. https://store.digilentinc.com/fpga-development-boards-kits-from-digilent/
Long wires might create ringing or cross-talk on/between the signals, 
With Digital Discovery for 8bit+1clock DDR you will have to capture 16 signals at 400MHz and up to 128Msamples.  This is suffice for 80Msamples of 125MHz DDR data, 128*2*125/400

[HoWei]

What is the maximum number of samples that can be capture in this setup ?

We would need ~2MBit, and we would need 8 DDR datalines to be captured (as mentioned above, its to read out the ADC 3421 from TI).

Is this doable ?

 

[HoWei]

Below I illustrated the expected results. 

The captured data should be as mentioned above, like a vector D=[0111 1100 0011 1111 1111 0101 10].

Having additional timestamps would be advantegous.

[Edit:] Oh wow I see in the above picture you implemented it already ! BusEither is what we want !

The ultimate goal is to have a python script that reads the DDR data from the Digital Discovery Box.

 

[HoWei]

Thanks for spending time and effort on my question - I very much appreciate that.

I am still trying to understand how this setup works - I will try to explain in my own words:

- Clock is the DDR clock with 100MHz (period=10ns) --> this results in 200MS/s, because each edge (rise/fall) determines one sample

- 0[MSB] is the DDR data which gets sampled by the DDR clock

- BusRise is the sampled data at the rising edges R=[0011 1100 0011 1111 1110 0001 10]

- BusFall is the sampled data at the falling edges F=[0111 1110 0001 1111 1111 1111 10]

- expected data are a multiplexed version of R[] and F[], like: R[n] ,F[n+1], R[n+2], F[n+3] ....  D=[0111 1100 0011 1111 1111 0101 10]

I do not see any logic function that would do this data calculation - only multiplexing would do it, right ?

 

 

 

[attila]

Hi @HoWei

I will release a beta version with above mentioned modification/additions next week.

[attila]

Hi @HoWei

At the moment a 100MHz DDR data interpretation looks like this:

I will update the WaveForms application in the following days to have for the Bus interpreter:
- either Clock edge option
- sampling delay relative to edge
- Events view to list sample for each edge when Clock signal is selected

Thank you for your questions

[HoWei]

Since I do not have a digital discovery box yet, I cannot test it, thus I have the follow-up question: 

How will the captured data look ?

Will it be time-samples (not what I want) -

or will it be samples per rise/fall-edge (what I want) ?

 

[attila]

Hi @HoWei

The bandwidth of the digital input lines on Digital Discovery is about 100MHz. This highly depends on the driver circuit and the wiring. With weak driver it may not be able to detect the signal correctly, capacitance of inappropriate wiring may also reduce the bandwidth, wiring could also cause cross-talk or ringing.

The sync capture mode tops at 100MHz for either-edge/ddr 50MHz, so the input signal frequency should be lower than this.

You may try to capture the 120Mhz signal with HS adapter in over-sampled mode at 400-800MHz, use two Bus interpreters one with Clock on Rising and the other one on Falling edge.

[HoWei]

Hi,

I found this answer, because I had the same question. I would like to get more detailed information about this device and its usability for my application.

I do have a ADC (ADC3421 from  TI) that provides a DDR_data output with 120MS/s and its corresponding 60MHz DDR_clock output.

I would like to use the Digital Discovery to capture the DDR_data for each rising/falling clock of DDR_clock. Advantageous would be, if the device provides digital data 0s and 1s, depending on a given threshold.

I would like to capture ~2MBit of data.

I do NOT want to start an oversampled waveform capture and post-process the oversampled data to find out the data for every edge. Instead, as described above, I want ONE datapoint per risign/falling DDR_clock edge.

 

Is that possible ?

What is the max. number of datapoints to be captured this way ?

 

I hope I could explain my requirements clearly - I am happy to answer all forther questions on my application.

 

[attila]

1. Yes. After installing the WaveForms application click on the SDK link to open the directory containing the Manual, Python/C examples, C#/VB wrappers, dwfcmd demo application.

2. Yes. See the SDK/ py/ DigitalIn_Sync.py example.
In the application you can capture based on internal 100-800MHz clock and use the bus clock option to interpret the data or use the Clock option with Sync mode like this:

3. The API returns 8, 16 or 32 bit samples which can be masked in the custom application/script like for 12 bit bus = sample & 0xFFF