MUX 2x1 using VHDL

[Jaiko007]

Hello, 

I need to design PWM for a multiplexer 2x1 for my project. The description is:

• If select = 0, output = input 1 (10kHz)
• If select = 1, output = input 2 (100kHz)

The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. 

mux2to1.vhd

mux2to1_tb.vhd

Thank you.

[sLowe]

Hey Jaiko,

On top of this module I would use the clocking ip wizard to generate these two frequencies. Once you do this, you can feed the two clocks into your mux. However, you may get some critical warnings about logic on clocks but since you are using them for PWM and not actual clocking, this should not affect your design. 

Hope this helps a bit!