PCAM OV5640 Power

[Sduru]

Hello All,

Is the CMOS OV5640 on PCAM PCB powered up directly from Zybo Z7? Do we need a special SDK project to trigger the OV5640 on PCAM? Can it work normally with its defaults settings from a simple hello world SDK apps? 

I mean that I cannot get OV5640 streaming through MIPI CSI-2 into Vivado ILA core although it is supplied 3.3V through FFC cable normally (I physically measured it). As you can see in the attachment, I am getting "no streams" warning in the waveform window of HW manager. Does anyone has an idea about this? Could it be related to some hardware/component problem on OV5650 or somewhere else PCAM? 

Best regards

Sami  

[jpeyron]

Hi @Sduru,

It sounds like you were able to get the PCAM-5C  working correctly as stated in your other thread here. 

Is that correct?

best regards,

Jon

 

[Sduru]

Hi @jpeyron

No, this is a different issue. I don't get any error, but also I don't get camera streaming!  Additionally, I can't get application options (change resolution or fps etc) in the terminal although everything seems OK. There is no hdmi output and no streaming into ila core of hw manager. If I Apply a hello world application, I am just getting hello world message in the Sdk terminal with no error!

I am not sure if it is a cmos hardware problem or a software problem. 

[jpeyron]

Hi @Sduru,

To clarify the situation,

You are using a Zybo Z7-20 with the updated to Vivado 2018.2 PCAM-5C project. You are not able to get streaming video or the serial terminal menu. 

What OS and serial terminal are you using? 

Please provide screen shots of your block design, wrapper and SDK Code.

best regards,

Jon

[Sduru]

Hi @jpeyron

1. I am using Zybo Z7-20 and Vivado 2018.2

2. I have generated bitstream normally with the updated version of Pcam application. I have imported sdk project with no problem and no error! 

3. I am using Windows 10 and tera term. Com-port is also currect.

4. I have just added an ila core to the block desing, and validated succussfully. I didnt make any other change. 

I am sorry but I am not able to share my screenshots at the moment. I can do it later but I summarized the situation above correctly.

Thanks

[Sduru]

Hello @jpeyron

SDK Application window is attached. As you can see, it is Connected to COM1 at 115200. But there is no serial terminal menu. 

Block design is also attached. The only difference from your origiinal design is ila core (validated). 

And finally, this is the wrapper:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
  port (
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_cas_n : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    cam_gpio_tri_io : inout STD_LOGIC_VECTOR ( 0 to 0 );
    cam_iic_scl_io : inout STD_LOGIC;
    cam_iic_sda_io : inout STD_LOGIC;
    dphy_clk_lp_n : in STD_LOGIC;
    dphy_clk_lp_p : in STD_LOGIC;
    dphy_data_hs_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_hs_p : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_p : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_hs_clock_clk_n : in STD_LOGIC;
    dphy_hs_clock_clk_p : in STD_LOGIC;
    hdmi_tx_clk_n : out STD_LOGIC;
    hdmi_tx_clk_p : out STD_LOGIC;
    hdmi_tx_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    hdmi_tx_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
end system_wrapper;

architecture STRUCTURE of system_wrapper is
  component system is
  port (
    dphy_clk_lp_n : in STD_LOGIC;
    dphy_clk_lp_p : in STD_LOGIC;
    dphy_data_hs_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_hs_p : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_n : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_data_lp_p : in STD_LOGIC_VECTOR ( 1 downto 0 );
    dphy_hs_clock_clk_p : in STD_LOGIC;
    dphy_hs_clock_clk_n : in STD_LOGIC;
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    cam_gpio_tri_i : in STD_LOGIC_VECTOR ( 0 to 0 );
    cam_gpio_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    cam_gpio_tri_t : out STD_LOGIC_VECTOR ( 0 to 0 );
    cam_iic_sda_i : in STD_LOGIC;
    cam_iic_sda_o : out STD_LOGIC;
    cam_iic_sda_t : out STD_LOGIC;
    cam_iic_scl_i : in STD_LOGIC;
    cam_iic_scl_o : out STD_LOGIC;
    cam_iic_scl_t : out STD_LOGIC;
    hdmi_tx_clk_p : out STD_LOGIC;
    hdmi_tx_clk_n : out STD_LOGIC;
    hdmi_tx_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    hdmi_tx_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  end component system;
  component IOBUF is
  port (
    I : in STD_LOGIC;
    O : out STD_LOGIC;
    T : in STD_LOGIC;
    IO : inout STD_LOGIC
  );
  end component IOBUF;
  signal cam_gpio_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cam_gpio_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cam_gpio_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cam_gpio_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cam_iic_scl_i : STD_LOGIC;
  signal cam_iic_scl_o : STD_LOGIC;
  signal cam_iic_scl_t : STD_LOGIC;
  signal cam_iic_sda_i : STD_LOGIC;
  signal cam_iic_sda_o : STD_LOGIC;
  signal cam_iic_sda_t : STD_LOGIC;
begin
cam_gpio_tri_iobuf_0: component IOBUF
     port map (
      I => cam_gpio_tri_o_0(0),
      IO => cam_gpio_tri_io(0),
      O => cam_gpio_tri_i_0(0),
      T => cam_gpio_tri_t_0(0)
    );
cam_iic_scl_iobuf: component IOBUF
     port map (
      I => cam_iic_scl_o,
      IO => cam_iic_scl_io,
      O => cam_iic_scl_i,
      T => cam_iic_scl_t
    );
cam_iic_sda_iobuf: component IOBUF
     port map (
      I => cam_iic_sda_o,
      IO => cam_iic_sda_io,
      O => cam_iic_sda_i,
      T => cam_iic_sda_t
    );
system_i: component system
     port map (
      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
      DDR_cas_n => DDR_cas_n,
      DDR_ck_n => DDR_ck_n,
      DDR_ck_p => DDR_ck_p,
      DDR_cke => DDR_cke,
      DDR_cs_n => DDR_cs_n,
      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
      DDR_odt => DDR_odt,
      DDR_ras_n => DDR_ras_n,
      DDR_reset_n => DDR_reset_n,
      DDR_we_n => DDR_we_n,
      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
      cam_gpio_tri_i(0) => cam_gpio_tri_i_0(0),
      cam_gpio_tri_o(0) => cam_gpio_tri_o_0(0),
      cam_gpio_tri_t(0) => cam_gpio_tri_t_0(0),
      cam_iic_scl_i => cam_iic_scl_i,
      cam_iic_scl_o => cam_iic_scl_o,
      cam_iic_scl_t => cam_iic_scl_t,
      cam_iic_sda_i => cam_iic_sda_i,
      cam_iic_sda_o => cam_iic_sda_o,
      cam_iic_sda_t => cam_iic_sda_t,
      dphy_clk_lp_n => dphy_clk_lp_n,
      dphy_clk_lp_p => dphy_clk_lp_p,
      dphy_data_hs_n(1 downto 0) => dphy_data_hs_n(1 downto 0),
      dphy_data_hs_p(1 downto 0) => dphy_data_hs_p(1 downto 0),
      dphy_data_lp_n(1 downto 0) => dphy_data_lp_n(1 downto 0),
      dphy_data_lp_p(1 downto 0) => dphy_data_lp_p(1 downto 0),
      dphy_hs_clock_clk_n => dphy_hs_clock_clk_n,
      dphy_hs_clock_clk_p => dphy_hs_clock_clk_p,
      hdmi_tx_clk_n => hdmi_tx_clk_n,
      hdmi_tx_clk_p => hdmi_tx_clk_p,
      hdmi_tx_data_n(2 downto 0) => hdmi_tx_data_n(2 downto 0),
      hdmi_tx_data_p(2 downto 0) => hdmi_tx_data_p(2 downto 0)
    );
end STRUCTURE;
 

[jpeyron]

Hi @Sduru,

Are you sure that the Zybo-Z7 is on COM1? Typically COM1 is an internal com port.

Also sometime the menu will not show initially. Did you try hitting the enter button? 

I typically use something like tera term or PuTTY. Have you tied using one of these serial terminal emulators instead of the SDK serial terminal emulator?

best regards,

Jon

[Sduru]

Hi Dear @jpeyron

I am %100 sure that Zybo-Z7 is on COM1. For that I have attached the screenshot of this com1 showing Digilent USB adapter on COM1. In addition to this, I am able to program the Xilinx device on Zybo-Z7 by using the same micro USB port. 

I have hit the enter button on both of Tera Term and SDK terminal, but it didn't solve the problem. It is not transmitting HDMI output from HDMI TX to my monitor. 

Moreover, I bought a new PCAM 5C PCB to see if there is a component problem on it. But nothing changed. 

[jpeyron]

Hi @Sduru,

I have reached out to more experienced engineers to see if they have more input for you about this thread. 

best regards,

Jon

[Sduru]

Hi @jpeyron

Thank you very much. I am looking forward to your response. 

Best regards..

 

[Ciprian]

Hi @Sduru,

In order to see data transfers on the AXI-Stream interface which is connected to the PCAM you will need to configure the PCAM and enable the DMA transfers to do so. This is accomplished using the SDK, therefor you will need to program and monitor the ILA as well as run the SDK program to see any changes on the ILA. I'm guessing that you have a problem with running the code which would explain why you don't see the menu on the console  or any traffic on the ILA.

I'm guessing that your terminal is set up properly (although using COM1 is unusual), because you mentioned that you ran a hello world project and it displayed the message on the terminal, which leaves us with the possibility that you either have an error running the code  in SDK or that there is a bug which does not allow you to get to the menu part of the PCAM code.

To test this please put a xil_printf("hello world\n"); at the beginning of the main function and check if it is displayed.

-Ciprian

[Sduru]

Hello Dear @Ciprian 

I've put xil_printf("hello world\n"); command at the beginning of the main function like in the attached screenshot with no additional changing. But SDK gave some strange errors. The error codes are also attached. Moreover, I run the project, nothing has been changed: It says it is connected to COM1 and there is no menu on the console  or any traffic on the ILA.  

[Ciprian]

Hi @Sduru,

These are BSP errors you will have to regenerate the bsp. Just right click on it in the project explorer (on the left of the main SDK windows) and hit Re-generate BSP sources. These are common xilinx SDK errors, not specific to this project.

-Ciprian

[Sduru]

Hi @Ciprian

I re-generated BSP sources, but the same errors like above still remain! The situation is the same: PCAM project code does not run and there is no menu on the console although it says it is connected to COM1. I am able to connect to COM1 with a simple hello world application and see the messages on the console over the same Vivado block design. 

Best regards...  

[vicentiu]

Can you send us the project to look at? It's hard to determine just by looking at the screenshot.