DDR3 input clock source

[mishu]

Hi,

I am wondering why is a 100 MHz clock present on the ARTY-S7 to be used for the DDR3 clocking, but not present in the ARTY-7.  Why not use only a single 100 MHz clock source for ARTY-S7 as main clocking source? Or this was the idea from the beginning?

I suppose in both cases with a SE 100 MHz clock source placed on a MRCC FPGA pin can be used to clock also the FPGA resources and the external DDR3 device. 

Cheers,

Mishu

[jpeyron]

Hi @mishu,

I believe we added the additional oscillator to help meet timing and eliminated propagation delays with the DDR3. I have reached out to a more experienced engineer to see if they have any additional input as well.

best regards,

Jon  

[malexander]

There is only a single 100MHz oscillator that's loaded (IC3). The other one (IC2) is not loaded. In order to meet timing the DDR reference clock and DDR system clock have to be in the same column as the bank that contains the DDR3 interface. I don't recall what the thinking was when we included the 12 MHZ USB clock (UCLK) that goes into Bank 15, but you should be able to clock the entire device from pin R2.