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DDR3 input clock source



I am wondering why is a 100 MHz clock present on the ARTY-S7 to be used for the DDR3 clocking, but not present in the ARTY-7.  Why not use only a single 100 MHz clock source for ARTY-S7 as main clocking source? Or this was the idea from the beginning?

I suppose in both cases with a SE 100 MHz clock source placed on a MRCC FPGA pin can be used to clock also the FPGA resources and the external DDR3 device. 



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