Tifei

JTAG boundary scan: Do BSDL file for Xilinx FPGA

Recommended Posts

Hi,

I read few messages on the forum but I would like to confirm if my understanding is right.

I have a Digilent JTAG HS-2 cable. I installed Digilent Adept 2. I have my Xilinx FPGA BSDL file. I installed Vivado.

Can I do boundary scan with above "weapons"? What I want to do is run BSDL to check my FPGA pin connectivity and to see if the FPGA is good or bad.

From the Forum research the answer is NO. Do I understand this correctly?

Please advice, thank you.

 

Share this post


Link to post
Share on other sites

Hi @Tifei,

I would guess you have seen this thread here. The adept software is not design to facilitate the usage of BSDL Files with the JTAG-HS2.  I would suggest reaching out to Xilinx about Vivado.

best regards,

Jon

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now