JTAG boundary scan: Do BSDL file for Xilinx FPGA


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Hi,

I read few messages on the forum but I would like to confirm if my understanding is right.

I have a Digilent JTAG HS-2 cable. I installed Digilent Adept 2. I have my Xilinx FPGA BSDL file. I installed Vivado.

Can I do boundary scan with above "weapons"? What I want to do is run BSDL to check my FPGA pin connectivity and to see if the FPGA is good or bad.

From the Forum research the answer is NO. Do I understand this correctly?

Please advice, thank you.

 

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