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Ufuk Keskin

Simulation problem in Vivado (BASYS3 SPI Implementation)

Question

I was intended to implement the code below in the simulation to connect it with Arduino where Arduino is master, BASYS3 is the slave:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SPI_rx2_top is
    Port ( clk: in STD_LOGIC;
           SCK  : in  STD_LOGIC;    -- SPI input clock
           MOSI : in  STD_LOGIC;    -- SPI serial data input
           SS   : in  STD_LOGIC;    -- chip select input (active low)
           MISO  : out STD_LOGIC;
           led: out STD_LOGIC_VECTOR(7 downto 0));
end SPI_rx2_top;

architecture Behavioral of SPI_rx2_top is
    signal dat_reg : STD_LOGIC_VECTOR (7 downto 0);
    signal dat_out : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
    signal sck_rise : STD_LOGIC;
    signal sck_fall : STD_LOGIC;
    signal sck_prev : STD_LOGIC;
    signal sck_forw : STD_LOGIC;
    signal sync_mosi : STD_LOGIC;
    signal sync_miso : STD_LOGIC;
    signal sync_ss: STD_LOGIC;
begin
process(clk,sync_ss,sck_rise,sck_fall) begin

if(rising_edge(clk)) then
    if(SCK /= sck_prev and SCK='1') then
    sck_rise <= '1' ;
    else sck_rise <= '0' ;
    end if;
    if(SCK /= sck_prev and SCK='0') then
    sck_fall <= '1' ;
    else sck_fall <='0' ;
    end if;
    sck_prev <= SCK ;
    sync_mosi <= MOSI;
    sync_ss <= SS;
    
    if (sck_rise = '1' and sync_ss= '0' ) then  -- rising edge of SCK
                -- shift serial data into dat_reg on each rising edge
                -- of SCK, MSB first
                dat_reg <= dat_reg(6 downto 0) & sync_mosi;
                else
                dat_reg <= dat_reg ;
            end if;
    dat_out<="11111111";
    if(sck_fall = '1' and sync_ss='0') then
                MISO <= dat_out(7) ;
                dat_out <=dat_out(6 downto 0) & '0' ;
                else
                dat_out <= dat_out;
        end if;
        end if;
    end process;
led <= dat_reg;
end Behavioral;

where I want to take 8 bit data from MOSI input when input clock "SCK" (since there is no compatible clock pin in BASYS3 I did the code detecting rising and falling parts) is in rising edge and input ss is '0' . But when I put it to a simulation it shows a weird result:

image.thumb.png.1106e384b3dfb701bbd589318f1322ae.png

I forced clk: 10ns (100MHz)

              SCK: 250ns (4MHz)

              MOSI: Force Constant 1,

             SS: 4us

But I can't get the data_reg as i expected. Since it collects all MOSI inputs, it should be "11111111" but it doesn't happen. What is the problem there?

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3 answers to this question

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Hi @Ufuk Keskin,

Could you attach your test bench? Right now your code looks like it is set up just so that the dat_out is being fed with the data and filling MISO (so your slave device, the Basys 3, would be sending out data) and the dat_reg is getting data from MOSI, which makes sense, but something is isn't quite right in your design. I would also recommend taking a look at this SPI design to reference to ensure everything is set up correctly.

Thanks,
JColvin

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On ‎5‎/‎16‎/‎2019 at 12:11 AM, JColvin said:

Hi @Ufuk Keskin,

Could you attach your test bench? Right now your code looks like it is set up just so that the dat_out is being fed with the data and filling MISO (so your slave device, the Basys 3, would be sending out data) and the dat_reg is getting data from MOSI, which makes sense, but something is isn't quite right in your design. I would also recommend taking a look at this SPI design to reference to ensure everything is set up correctly.

Thanks,
JColvin

Hi @JColvin,

I haven't prepared a test bench, I am setting all values on the simulation window as I have stated in the first post. The design you have referred seems to be designed for fpga as a master, but I want to use it as a slave, so i am not sure it does help.

Thanks,

Ufuk Keskin

 

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Hi @Ufuk Keskin,

The same github user has a SPI slave version here: https://github.com/Nematollahi/SPI-FPGA-VHDL/blob/master/hdl/spi_slave.vhd.

Additionally, remember that in HDL, everything happens simultaneously rather than sequentially so the HDL you have written where you assign data_out as all 1's and then in following line assign data out to one of two options can potentially happen at the same time; so I believe the resulting circuit that is implmented when the code is synthesized will not assign dat_out as all ones and then check the if statement after that.

Thanks,
JColvin

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