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Tim S.

Zybo Z7-20 audio interrupt

Question

I have merged the Pcam5C and DMA projects to gain an understanding of the IP Integrator and Xilinx SDK.

I am not receiving an interrupt on s2mm_introut of axi_dma_0 of the sound DMA part of the example.

In main.cc, I have merged-in the demo.c main procedure.

irpt_ctl.registerHandler(XPAR_FABRIC_AXI_GPIO_0_IP2INTC_IRPT_INTR, reinterpret_cast<typename ScuGicInterruptController::Handler>(&fnUserIOIsr), &sUserIO);

irpt_ctl.registerHandler(XPAR_FABRIC_AXI_IIC_0_IIC2INTC_IRPT_INTR, reinterpret_cast<typename ScuGicInterruptController::Handler>(&XIic_InterruptHandler), &sIic);

irpt_ctl.registerHandler(XPAR_FABRIC_AXI_DMA_0_MM2S_INTROUT_INTR, reinterpret_cast<typename ScuGicInterruptController::Handler>(&fnMM2SInterruptHandler), &sAxiDma);

irpt_ctl.registerHandler(XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR, reinterpret_cast<typename ScuGicInterruptController::Handler>(&fnS2MMInterruptHandler), &sAxiDma);

irpt_ctl.enableInterrupts();

To use the same ScuGicInterruptController.h already provided by the Pcam5C, I have added a call to XScuGic_SetPriorityTriggerType().

	template <typename ...Arg>
	Errc registerHandler(uint32_t irpt_id, Handler handler, Arg&& ...args)
	{
		XStatus Status;

		Status = XScuGic_Connect(&drv_inst_, irpt_id,
		   (Xil_InterruptHandler) handler,
		   std::forward<Arg>(args)...);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		//Enable the interrupts for the IIC device.
		this->enableInterrupt(irpt_id);
//		XScuGic_Enable(&drv_inst_, irpt_id);

		return XST_SUCCESS;
	}
	Errc disableInterrupt(uint32_t irpt_id)
	{
		XScuGic_Disable(&drv_inst_, irpt_id);
		return XST_SUCCESS;
	}
	Errc enableInterrupt(uint32_t irpt_id)
	{
		XScuGic_SetPriorityTriggerType(&drv_inst_, irpt_id, 0x00, 0b11);
		XScuGic_Enable(&drv_inst_, irpt_id);
		return XST_SUCCESS;
	}

I receive an interrupt that writes to Demo.fDmaMM2SEvent, but no interrupt that writes to Demo.fDmaS2MMEvent. Thus the recording never completes; but playback does complete without a recording.

I need to understand how to display the Zynq 7 Processing System ARM-9 interrupt registers and Xilinx AXI DMA status/control registers in the SDK Debug Perspective. I also need to understand the necessity of XScuGic_SetPriorityTriggerType for adding edge/level with priority configuration, of peripheral IRQs. Where can I find relevant documentation besides AXI DMA IP product guide?

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3 answers to this question

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Hi @Tim S.,

We do not have more in depth guides or documentation that would better describe using the xilinx drivers. I would suggest looking C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers at to better understand how xilinx uses their IP cores.

We would also suggest reaching out to Xilinx support about using their drivers as well.

best regards,

Jon

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Hi @jpeyron,

I have examined some of the d_axi_i2s_audio Digilent IP Core sources. It appears that the control of the fifo_4 and fifo_32 fifo instances might be dependent on the AXI4 Stream and AXI4 Lite all running on the same clock. I had attempted to run the AXI4 Lite at 50 MHz and the AXI4 Stream run at a matching-phase 100 MHz. Best I can tell from the STATUS register is that the FIFOs fill with data and then are not dequeued. If I utilize a second M_GP (M_GP1) on the Zynq 7 Processing System and execute it at 100 MHz instead of 50 MHz; and interconnect the Audio DMA cores all at the same 100 MHz; then the audio I2S functions according to the Audio DMA example.

Best regards,

Tim

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