1. I am using nexys video to read analog values but output is showing zero in UART terminal. I have used verilog code mentioned in UG 480 v1.10.1. I am using ISE 14.4 and XADC IP core . I did a slight change in code by setting clk divide to 8 instead of 4 since nexys video has 100 Mhz clock. Secondly, i have enable VCCINT channel only.
2. Secondly in automatic channel sequencer we have to wait for drdy only and read data from do_drp of the selected channel ? No need to write data initially through DRP since it is initialized in IP core ?
3. ADC top module is shown below and IP core code is attached:
always @ (posedge clk or negedge arst_n)
if (arst_n) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
end
else
case (state)
init_read :
if (busy == 0 )
state <= read_reg01;
read_reg01 : begin
daddr <= 7'h01;
den_reg <= 2'h2; // performing read
state <=reg01_waitdrdy;
end
reg01_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCINT <= do_drp;
state <=read_reg01;
daddr <= 7'h01;
end
else begin
den_reg <= { 1'b0, den_reg[1] } ;
dwe_reg <= { 1'b0, dwe_reg[1] } ;
state <= state;
end
Question
Bilal29
1. I am using nexys video to read analog values but output is showing zero in UART terminal. I have used verilog code mentioned in UG 480 v1.10.1. I am using ISE 14.4 and XADC IP core . I did a slight change in code by setting clk divide to 8 instead of 4 since nexys video has 100 Mhz clock. Secondly, i have enable VCCINT channel only.
2. Secondly in automatic channel sequencer we have to wait for drdy only and read data from do_drp of the selected channel ? No need to write data initially through DRP since it is initialized in IP core ?
3. ADC top module is shown below and IP core code is attached:
`timescale 1ns / 1ps
module ADC_TOP(
input clk,
input arst_n,
output reg [15:0] MEASURED_VCCINT
);
reg [6:0] daddr;
reg [1:0] den_reg;
reg [15:0] di_drp;
reg [1:0] dwe_reg;
wire [15:0] do_drp;
wire drdy;
reg [7:0] state;
parameter init_read = 8'h00,
read_waitdrdy = 8'h01,
write_waitdrdy = 8'h03,
read_reg01 = 8'h06,
reg01_waitdrdy = 8'h07;
ADC_IP_Core UUT_ADC_IP
(
.DADDR_IN(daddr),
.DCLK_IN(clk),
.DEN_IN(den_reg[0]),
.DI_IN(di_drp),
.DWE_IN(dwe_reg[0]),
.RESET_IN(arst_n),
.BUSY_OUT(busy),
.CHANNEL_OUT(),
.DO_OUT(do_drp),
.DRDY_OUT(drdy),
.EOC_OUT(),
.EOS_OUT(),
.ALARM_OUT(),
.VP_IN(),
.VN_IN()
);
always @ (posedge clk or negedge arst_n)
if (arst_n) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
end
else
case (state)
init_read :
if (busy == 0 )
state <= read_reg01;
read_reg01 : begin
daddr <= 7'h01;
den_reg <= 2'h2; // performing read
state <=reg01_waitdrdy;
end
reg01_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCINT <= do_drp;
state <=read_reg01;
daddr <= 7'h01;
end
else begin
den_reg <= { 1'b0, den_reg[1] } ;
dwe_reg <= { 1'b0, dwe_reg[1] } ;
state <= state;
end
endcase
endmodule
ADC_IP_Core.v
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