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Nexys Video XADC in ISE 14.4 using XADC IP Core


1. I am using nexys video to read analog values but output is showing zero in UART terminal. I have used verilog code mentioned in UG 480 v1.10.1. I am using ISE 14.4 and XADC IP core .  I did a slight change in code by setting clk divide to 8 instead of 4 since nexys video has 100 Mhz clock. Secondly, i have enable VCCINT channel only.

2. Secondly in automatic channel sequencer we have to wait for drdy only and read data from do_drp of the selected channel ? No need to write data initially through DRP since it is initialized in IP core ? 

3. ADC top module is shown below and IP core code is attached:


`timescale 1ns / 1ps

module ADC_TOP(

input clk,
input arst_n,
output reg [15:0] MEASURED_VCCINT

reg [6:0] daddr;
reg [1:0] den_reg;
reg [15:0] di_drp;
reg [1:0] dwe_reg;
wire [15:0] do_drp;
wire drdy;

reg [7:0] state;
parameter init_read = 8'h00,
read_waitdrdy = 8'h01,
write_waitdrdy = 8'h03,
read_reg01 = 8'h06,
reg01_waitdrdy = 8'h07;


always @ (posedge clk or negedge arst_n)
if (arst_n) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
case (state)

init_read :
if (busy == 0 )
state <= read_reg01;

read_reg01 : begin
daddr <= 7'h01;
den_reg <= 2'h2; // performing read
state <=reg01_waitdrdy;

reg01_waitdrdy :
if (drdy ==1) begin
state <=read_reg01;
daddr <= 7'h01;
else begin
den_reg <= { 1'b0, den_reg[1] } ;
dwe_reg <= { 1'b0, dwe_reg[1] } ;
state <= state;



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Hi @Bilal29,

I do not have any experience using the XADC in ISE.  Hopefully one of the more experienced community members will have some input for you in regards to ISE and the XADC.

Is there a specific reason you are using ISE instead of Vivado?

After re-reading your previous thread. If you were to use Vivado you can view the fpga temperature from the Hardware Manager in Vivado. Viewing the temperature is discussed and shown in this forum thread here.  

We also have a complete and verified XADC project or the Nexys Video on resource center here using Vivado. 

best regards,


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Can you please share complete verilog top module code of ADC. Verilog code will be same whether we use ISE or vivado ! 

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Ip core data is not present. Dont what they have initialized with. Like:

        .INIT_40(16'h9000), // config reg 0
        .INIT_41(16'h2fff), // config reg 1
        .INIT_42(16'h0800), // config reg 2
        .INIT_48(16'h0200), // Sequencer channel selection
        .INIT_49(16'h0000), // Sequencer channel selection
        .INIT_4A(16'h0000), // Sequencer Average selection
        .INIT_4B(16'h0000), // Sequencer Average selection
        .INIT_4C(16'h0000), // Sequencer Bipolar selection
        .INIT_4D(16'h0000), // Sequencer Bipolar selection
        .INIT_4E(16'h0000), // Sequencer Acq time selection
        .INIT_4F(16'h0000), // Sequencer Acq time selection
        .INIT_50(16'hb5ed), // Temp alarm trigger
        .INIT_51(16'h57e4), // Vccint upper alarm limit
        .INIT_52(16'ha147), // Vccaux upper alarm limit
        .INIT_53(16'hca33),  // Temp alarm OT upper
        .INIT_54(16'ha93a), // Temp alarm reset
        .INIT_55(16'h52c6), // Vccint lower alarm limit
        .INIT_56(16'h9555), // Vccaux lower alarm limit
        .INIT_57(16'hae4e),  // Temp alarm OT reset
        .INIT_58(16'h5999), // VBRAM upper alarm limit
        .INIT_5C(16'h5111),  //  VBRAM lower alarm limit

Only below mentioned code is present with top module. It is incomplete. Ug 480 include all code but it is not working.

xadc_wiz_0 XADC (




















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Hi @Bilal29,

Here is a XADC VHDL project  for the basys 3( can be altered to work with the nexys video) done by one of our community members @hamster that uses the XADC IP instead of the XADC wizard as you are looking to do. Sorry for the inconvenience. 

best regards,


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