I am trying to follow the 'Getting Started with IP Integrator' tutorial provided by Digilent with the Genesys2 FPGA boards, and despite it seeming like a simple tutorial, I can't get it working at all.
It looks like the on-board LEDs aren't being routed to the correct pins once I run the implementations.
While following the tutorial, adding the IP, and configuring it works well. When installing Vivado on my Windows 10 machine, I downloaded the board files from Digilent following their tutorial as well. I can see the Genesys2 board upon creating the project, so I don't see the issues coming from there.
Aside from following that tutorial to a T, I also changed the clock IO Standards in the part0_pins board file to 'LVDS' as implementation was not operating properly without that - complaining about the wrong IO standard. The change has been attached to this post.
The errors I get from the messages window have also been attached to this post, and appear when the bitstream generation fails. After reading the messages and 'googling' around, users said that those errors arise when pins aren't being fixed to a package pin. I then searched around the implementation, and notice that there's a bank called led_8bits_tri_i, in the I/O ports page, that are being suspiciously mapped as inputs, all to the correct package pins. I expect the error messages are coming from the led_8bits_tri_o ports, which aren't being mapped at all.
I'm not sure how to remap them, as I've tried superseding the board files with XDC files, yet the mapping issues persist.
If anyone has experienced this before, or could provide some insight, that would be greatly appreciated,
Question
Justen
I am trying to follow the 'Getting Started with IP Integrator' tutorial provided by Digilent with the Genesys2 FPGA boards, and despite it seeming like a simple tutorial, I can't get it working at all.
It looks like the on-board LEDs aren't being routed to the correct pins once I run the implementations.
While following the tutorial, adding the IP, and configuring it works well. When installing Vivado on my Windows 10 machine, I downloaded the board files from Digilent following their tutorial as well. I can see the Genesys2 board upon creating the project, so I don't see the issues coming from there.
Aside from following that tutorial to a T, I also changed the clock IO Standards in the part0_pins board file to 'LVDS' as implementation was not operating properly without that - complaining about the wrong IO standard. The change has been attached to this post.
The errors I get from the messages window have also been attached to this post, and appear when the bitstream generation fails. After reading the messages and 'googling' around, users said that those errors arise when pins aren't being fixed to a package pin. I then searched around the implementation, and notice that there's a bank called led_8bits_tri_i, in the I/O ports page, that are being suspiciously mapped as inputs, all to the correct package pins. I expect the error messages are coming from the led_8bits_tri_o ports, which aren't being mapped at all.
I'm not sure how to remap them, as I've tried superseding the board files with XDC files, yet the mapping issues persist.
If anyone has experienced this before, or could provide some insight, that would be greatly appreciated,
Thanks,
Justen
part0_pins.xml
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