Genesys 2 DDR3 MIG Constraints

[SeanS]

I am using the Genesys 2 board and I have added the mig.prj core file to the Vivado project.  However, when I run synthesis and implementation, check timing reports the DDR3_dqs_p[*] pins as having no input delay with a critical warning level of 'high'.

I realize the mig.prj is supposed to have the timing constraints embedded in it.

What should I do about this critical warning? 

-Sean

[jpeyron]

Hi @SeanS,

We reached out to one of our co-workers about this thread and they believe that this warning can be ignored.  We have also reached out to more experienced engineers about this thread as well.

best regards,

Jon

[SeanS]

Ok.  Thanks.

[jpeyron]

Hi @SeanS,

I heard back from our more experience engineers and they responded that if the MIG design guidelines are met, the interface is considered verified. As discussed in this xilinx forum thread.

The DQS signals are strobe/clock signals and due to the particularities of the DDR3 interface they are delayed internally during calibration. No static timing check is necessary.

For a final check you could create a MIG design for a Xilinx dev board and see if the same warning is given there.  If yes, then it is expected behavior.

best regards,

Jon