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Arty A7 - DDR from VHDL (not MicroBlaze)


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Is there an example project that interacts with the Arty A7 DDR memory directly from VHDL?    I have a potential image processing project that needs 16MB of memory accessible from processing in VHDL.  The incoming image rate exceeds 60MB/sec; this presents numerous challenges - a place to store intermediate images is the current concern.   Although I have DDR working with MicroBlaze, the processing rate exceeds accessing the DDR through MicroBlaze.  If not for the ARTY A7, I would consider shifting the project to the ZYBO Z7 or some other XILINX board, including one with sufficient SRAM.

Thanks,
Dave

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@aadgl,

I don't really have any tutorials on how to do this, but I do have an example including some documentation on how to set up the example.  Using the example, I can access the memory from a Wishbone bus.  The basic operation is: (some wishbone master, either CPU, DMA, or whatever) -> (WB to AXI bridge) -> (MIG controller with an AXI front end) -> external memory pins.  You can find this project here, and its documentation here.

Dan

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