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richilarro

very basics: how to use UART1 in zybo zynq-7000?

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Hi, sorry if I'm making a very basic question;

I want to use a uart protocol to send data to-from a PC, using the j11 USB/UART-JTAG connector on a Zybo Zynq7000. Simply put, my problem is that I don't know where to map the tx/rx wires.

In other boards it is clear which pins I should use. In the zynq-7000, the Zybo-Master.xdc file does not have these (only clock, PMODs, leds, switches and buttons). From the zybo Reference manual (page 12), MIO48 and MIO48 are the 1.8V tx-rx pins that receive the serial data converted from the USB packets through the FT2232HQ USB-UART bridge. The problem is that I cannot access those pins.

My source is a simple, generic UART code in verilog. I'm using VIVADO. I've tried to create a Block design, enabling the UART1 on the ZYNQ7 Processing System and exporting the xdc file, but apparently it is forbidden to place any wire on the C12 and B12 sites (the physical pins for the MIO 48&49, if I understood correctly.

Essentially what I need is a tutorial to create a project in verilog to communicate via the serial port available at the USB bridge.

Thanks for any help,

 

Miguel

 


 

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Hello,

You can see the TX RX locations either in the schematic or in the XDC that we provide.

In order to send data to the PC you can simply use the board's Micro USB connector (the same one used for programming). Here is a demo project which uses UART to send data to the PC.

Also, when creating a project, you should use the board files. This way Vivado will automatically use the correct constraints for the board and it will help you speed up the project configuration. 

Let us know if you are still having trouble.

Sergiu

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Thank you Sergiu for all the info. I may be confused but I could not find a single reference to TX-RX /uart/etc, on the XDC file. On the schematic it shows the pins MIO 48 and 49, which are unaccessible. If I just naively add: 

set_property PACKAGE_PIN B12 [get_ports {tx}]
set_property IOSTANDARD LVCMOS18 [get_ports {tx}]

I get the error message: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["D:/Users/richi/ZYBO/uart/uart.srcs/constrs_1/new/zybo_uart1.xdc":416]

Probably, since the UART 1 is coupled to the PS I should build an IP block first, but I was not able to find this instance (UART) within the demo project you linked. Maybe it is indeed a problem still beyond my limited knowledge. I will try to learn a bit more and then re-read this. :-)  Thank you anyway.

Best regards,

Miguel

 

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Sorry for confusing you, my answer was not quite correct.

The UART in this case has nothing to do with the UCF or the schematic, it is entirely controlled from the ZYNQ PS.

In order to use UART you will have to activate it in Vivado. Open the Block Design where you should see the ZYNQ PS, double click on it and then go to "MIO Configuration" and in the "I/O Peripherals" menu you have to check UART 1. UART 1 works on MIO 48 and 49.

After that you can go to "PS-PL Configuration" -> General where you can set the baud rate.

When this is completed you can go to SDK.

Sergiu

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hi @jperyron ,

i basically want to use only ps side of zynq , for uart communication between zybo and pc, so for this i took zynq 7 ps ip, then i create hdl wrapper , now i just want to know what things are necessary while writing program in sdk.

thank you , for replying to my question......

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Hi @Ram,

You can use the hello world template in sdk to see how to use the uart or the tutorial i linked above also uses the uart to communicate to a pc with sdk.Also i would suggest something like tera term on the pc as the serial terminal for communication.

Thank you,

Jon

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hi @Jon

the above mentioned tutorial is perfectly working,," thank you ", for that .

now my next task is to use only ps side of zynq,, it means i don't want to use axi -gpio(basically i disabled the ps from pl section)

so, after launch sdk , i am writing code for this , but it is not working,,,can you pls help me regarding this issue......

thank you

Ram

zynq_7_ps.PNG

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Hi @Ram,

I attached below a block design,  sdk code and tera term showing communication to the pc. I use the zybo board files when creating the project. The did block automation and the clicked into the zynq ip block design and removed all but the uart connection. Then i connect the FCLK_CLK0 to the M_AXI_GP0_ACLK. I them created a wrapper and generated a bitstream. Then exported the hardware including the bitstream and launched sdk. In sdk i created an application using the hello world template. If you are trying to use the usb otg here is a forum thread that will explain why this will not work with out using a embedded linux platform like petalinux.

thank you,

Jon

zybo_uart.jpg

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hi@jon

the uart usb in sdk tutorial was excellent , 

i have one question in my mind , can we use spi in place of uart

 

 

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On ‎3‎/‎30‎/‎2016 at 10:38 AM, Sergiu said:

Sorry for confusing you, my answer was not quite correct.

The UART in this case has nothing to do with the UCF or the schematic, it is entirely controlled from the ZYNQ PS.

In order to use UART you will have to activate it in Vivado. Open the Block Design where you should see the ZYNQ PS, double click on it and then go to "MIO Configuration" and in the "I/O Peripherals" menu you have to check UART 1. UART 1 works on MIO 48 and 49.

After that you can go to "PS-PL Configuration" -> General where you can set the baud rate.

When this is completed you can go to SDK.

Sergiu

Hello,

I am also trying to use UART. But I want to access UART from the Microblaze instance of the Zybo FPGA. Please let me know how it can be done.

Regards,

Avinash

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16 minutes ago, jpeyron said:

Hi @Avinash,

Welcome to the forums! I have not used Microblaze in a Zynq design as of yet. Here is a non-digilent tutorial Hello World on Microblaze UART on PS in Zynq Processor that discussed doing this that should be helpful.

thank you,

Jon

Thank you. This seems like a solution that could work. I am actually trying to get FreeRTOS on Microblaze in Zynq FPGA. Do you also have any references for me to achieve this.

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Hi @Avinash,

Here is a Avnet forum thread that discusses this but no response.  I have no experience with this topic. You might also want to reach out to FreeRTOS and Xilinx support about this question.

thank you,

Jon

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