I am using Vivado 2018.3 and a XC7A100T Artix-7. My project includes a Microblaze and an AXI QSPI controller. I am attempting to boot an SREC from Spansion Flash (S25FL256L) using the SREC SPI Bootloader. My SREC file size is around 830 KB. It takes over 2 minutes for the bootloader to finish loading the SREC. I commented out the VERBOSE definition, so nothing is being printed. Stack and heap sizes for the Bootloader are 2KB.
Does anyone have an idea as to how can I reduce this time?
I have tried increasing the clock frequency that is connected to my AXI QSPI controller (ext_spi_clk), but this did not help. I have also tried changing the bitstream configuration settings, but apparently that is for the initial FPGA configuration. I even tried an ELF bootloader found on Github, but it gave an error saying that my ELF header is invalid.
Has anyone found a solution to this problem? I have seen several posts on these forums regarding this, but have found no clear solutions...
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bhall
Hello,
I am using Vivado 2018.3 and a XC7A100T Artix-7. My project includes a Microblaze and an AXI QSPI controller. I am attempting to boot an SREC from Spansion Flash (S25FL256L) using the SREC SPI Bootloader. My SREC file size is around 830 KB. It takes over 2 minutes for the bootloader to finish loading the SREC. I commented out the VERBOSE definition, so nothing is being printed. Stack and heap sizes for the Bootloader are 2KB.
Does anyone have an idea as to how can I reduce this time?
I have tried increasing the clock frequency that is connected to my AXI QSPI controller (ext_spi_clk), but this did not help. I have also tried changing the bitstream configuration settings, but apparently that is for the initial FPGA configuration. I even tried an ELF bootloader found on Github, but it gave an error saying that my ELF header is invalid.
Has anyone found a solution to this problem? I have seen several posts on these forums regarding this, but have found no clear solutions...
Thanks in advance,
Brad
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