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jrosengarden

Use of Packaged IP causing critical errors

Question

Hi All;

I've created a packaged IP for a 4bit adder (Vivado 2018.3).  Mostly an exercise in learning to make sure I know what I'm doing when I start packaging up truly needed IP's.

The packaging of the IP from the project went fine, no issues.

Using the newly created IP in a new project works fine with an exception;  During the implementation run 27 critical errors pop up.  Each of these errors point to an uncommented line in the constraint file.  However, once the implementation is done I then build the bitstream, program the board (Basys3) and....**POOF** everything is working fine.  So the 27 critical errors don't cause a 'show stopper'.

I'd like to figure out WHAT is causing these errors so I can resolve the problem and not have this issue propagated thru the IP's I create for use in other projects.

See the attached image.

Any hints, guidance, suggestions (or answers) would be greatly appreciated.

Thanks

Screen Shot 2019-05-01 at 5.20.17 PM.png

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Posted (edited)

Vivado is complaining that there are active (not commented) pins in the constraint file that do not have matching port names in your design.

Open your design_1_wrapper.v file and reconcile the port names specified there with the constraints file.

It is not uncommon to have to change the name of a pin in the constraints file to match the port name in the wrapper. This could happen for example if you used "Make external" on an i/o pin from an IP block.

One thing that has helped in the past was to delete the top level wrapper and regenerate it. Sometimes when you make pins external after generating the wrapper, there can be inconsistencies between port and pin naming.

Xilinx UG903, page 42 and following elaborates on the scoping mechanism Vivado uses.

Edited by kwilber

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