This forum has been very helpful for me as I slowly come up to speed with Vivado. I now have a new question that I hope somebody can either answer or point me in the right direction;
In the attached image I have taken my full_adder RTL module and deployed it within a new project where I am using the IP Integrator. I have successfully implemented a 2 bit adder out of my original 1 bit full_adder. What is depicted in the image, below, is working fine. HERE IS MY PROBLEM: I can't seem to connect up a vector port to the a inputs, the b inputs or the s outputs. The only way I've been able to get it to work properly is to connect up individual (make external) ports on each instantiation of the full_adder. I would prefer using a[1:0], b[1:0] and s[1:0] but I run into 2 problems:
1). when I create a vector port for input a (a[1:0]) and b (b[1:0]) it seems that Vivado is tying both a ports together. Whatever it's doing - when I use vector ports for input a and b the design doesn't work.
2) when I create a vector port for output s (s[1:0]) it will only let me "hook up" one, or the other, of the s ports...but not both.
As stated above, the design as shown works...but only because I used individual input/output ports. Doing this manually when I've jumped it up to a 64 bit, 2's complement, adder is going to be problematic if I can't figure out how to use vector ports in the IP integrator. (NOTE: I've already done this, successfully, via pure Verilog code, starting with a 1/2 adder, then including that RTL design in the full adder, then including that RTL design in a 4 bit adder, then including that RTL design in a 16 bit adder...etc., etc., etc.). I'm trying to replicate this in the IP Integrator for "learning" purposes.
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jrosengarden
Hi All:
This forum has been very helpful for me as I slowly come up to speed with Vivado. I now have a new question that I hope somebody can either answer or point me in the right direction;
In the attached image I have taken my full_adder RTL module and deployed it within a new project where I am using the IP Integrator. I have successfully implemented a 2 bit adder out of my original 1 bit full_adder. What is depicted in the image, below, is working fine. HERE IS MY PROBLEM: I can't seem to connect up a vector port to the a inputs, the b inputs or the s outputs. The only way I've been able to get it to work properly is to connect up individual (make external) ports on each instantiation of the full_adder. I would prefer using a[1:0], b[1:0] and s[1:0] but I run into 2 problems:
1). when I create a vector port for input a (a[1:0]) and b (b[1:0]) it seems that Vivado is tying both a ports together. Whatever it's doing - when I use vector ports for input a and b the design doesn't work.
2) when I create a vector port for output s (s[1:0]) it will only let me "hook up" one, or the other, of the s ports...but not both.
As stated above, the design as shown works...but only because I used individual input/output ports. Doing this manually when I've jumped it up to a 64 bit, 2's complement, adder is going to be problematic if I can't figure out how to use vector ports in the IP integrator. (NOTE: I've already done this, successfully,
via pure Verilog code, starting with a 1/2 adder, then including that RTL design in the full adder, then including that RTL design in a 4 bit adder, then including that RTL design in a 16 bit adder...etc., etc., etc.). I'm trying to replicate this in the IP Integrator for "learning" purposes.
Thanks for any help/guidance/advice in advance.
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