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Jaiko007

Frequency Divider using VHDL

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Hi Jaiko07

What is specification for your output that you are aiming for?

It is is a 50% duty cycle, 200Hz signal then this might be a better pattern to follow for your process:

 

    countClock: process(clock,clear)
    begin
        if (clear = '1') then
            adjfreq <= "000000000000000000";
        elsif(clock'event and clock = '1') then
            -- Flip a the output once every 125,000 cycles (400Hz)
            -- to give a 200Hz output with 50% duty cycle
            if (adjfreq = "011110100001001000") then  
                adjfreq <= "000000000000000000";
                adjclock <= not adjclock;
            else 
                adjfreq <= adjfreq+1;
            end if;
        end if;
    end process;

I haven't compiled it or tested it, but the intent should be clear - you are counting the cycles between the transitions, then flipping the output. 

 

Edited by hamster

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Oh, and in the test bench this looks a little off:

 

   constant clock_period : time := 40 ns;  --50MHz

40 ns isn't 50 MHz :blink:

Edited by hamster

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