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Advices on demoboard and data trasmission

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Dear All,

For a university project, I am designing the readout electronics for a CCD sensor. I have just a little bit of experience with FPGAs so I need some advice.

The detector will have a quite slow pixel rate, maximum a 1 MHz and I will sample it with a 16bit ADC. I (hope) know how to implement the clocking and the ADC interface but I have no ideas on how to transfer the images to the PC.

I am planning to scan continuously the detector and when the FPGA receives a trigger it stores an image in a RAM block, after that I don't know how to transfer the content of the RAM to the computer. Originally I simply tough to use a UART (I do not care about the speed, it can take also tens of seconds to transfer an image) but with a UART I can transmit only 8 bits at a time. I also considered the possibility to use a USB FIFO, but I would minimize the electronics as much as possible and use as much as I can the electronics on the demo board (by the way, I am planning to use an Arty A7).

There is also the possibility to use the ethernet and a MicroBlaze, but it sounds a little bit complex and I do not really know where to start.

What do you suggest?

The scope of the project is focused more on the CCD and electronics side, so I should find a simple to implement solution for the communication.

 

Thank you!

Cheers

 

PS

Do you think that the Arty A7 is enough?

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Hi,

I'd stay clear of Ethernet for the time being. UART (and you may even omit the "Receiver" part, just use the "Transmitter") is much more straightforward. Transmit four bits at a time using hex notation 0-9, A-F. Terminate one 16-bit "frame" with a newline. Then you can simply view the output in a terminal window e.g. use Teraterm.

The problem you're describing can be solved in a few pages of Verilog if you know what you're doing (But, don't underestimate the difficulty of getting there... I don't think the Microblaze route means any less work). The BRAM is conveniently dual-port, so you can use one port for writing and one for reading.

A state machine could look like this:

- wait until ADC has written to the end of memory and stop it

- a) get 16-bit word from memory into a shift register

b) - wait for UART idle

- send the highest four bits

- shift the shift register 4 bits to the left

- goto b) 3 times

- wait for UART idle

- send newline

- increase memory pointer

- goto a) as many times as you have frames to transmit

- wait for UART idle

- send newline (to separate two chunks of data with a blank line)

- repeat infinitely

 

 

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... and this could be used as "UART" (minus the "R")

module serialTx(clk, out_tx, in_byte, in_strobe, out_busy);
   parameter nBitCycles = 0; // set this according to the desired baudrate (e.g. 100 MHz clock, 9600 baud => use 100e6/9600)

   input clk;
   output out_tx;
   input [7:0] in_byte;
   input       in_strobe;
   output      out_busy;
   
   reg [31:0] count;   
   reg [3:0]  state = 0;   
   reg [7:0]  data;   
   
   assign out_tx = (state == 0) ? 1'b1:    // ready
		   (state == 1) ? 1'b0:    // start bit
		   (state == 10) ? 1'b1:    // stop bit
		   data[0];                // data bits    
   assign out_busy = (state != 0);   
   
   always @(posedge clk) begin
      if (in_strobe) begin
	 count <= nBitCycles;
	 state <= 1;
	 data <= in_byte;
      end else if (state != 0) begin
	 if (count == 0) begin
	    count <= nBitCycles; // (non-final)
	    state <= state + 1; // (non-final)
	    case (state)
	      1: begin 
		 // startbit
	      end
	      default: begin 
		 // data bits
		 data <= {1'bx, data[7:1]};	       
	      end
	      10: begin
		 // stop bit
		 state <= 0;
		 count <= 'bx;
		 data <= 'bx;		 
	      end
	    endcase
	 end else begin
	    count <= count - 1;
	 end
      end
   end
endmodule

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Posted (edited)

I was about to suggest looking in the Project Vault where there are a few examples of UART transmitters... and then up popped the Verilog one from xc6lx45. If VHDL is more to your liking there are several in the Vault. The UartDebuggerR3.zip has mine (you also get a testbench example for simulation if you've never done that). I'm not making a negative comment about the implementation above ( it does present the idea in an easy to understand manner ) but some free stuff costs less that other free stuff. While you might only need a transmitter to do the project a full-blown UART with a receiver might be useful for debugging your design.

I agree that the UART is the easiest way to get a communications link going between a PC and your FPGA board and is more than adequate for most student projects. Python with PySerial makes creating a serial UART application easy. Have fun!

[edit] you can instantiate Verilog modules in your VHDL code and visa versa so find something that works for you regardless of the HDL

Edited by zygot

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yes, and I'm sure there are nicer ones... if you pick another one, one easy way to bring up a UART is to wire the FPGA-side input to the FPGA-side output e.g. "plus one" (and the rx strobe / tx send wire). Then open teraterm, type an "a" and you should get a "b" etc.

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Posted (edited)
15 minutes ago, xc6lx45 said:

open teraterm, type an "a" and you should get a "b" etc

Or Carriage Return and get Shift Out or send a Line Feed and get a Vertical Tab.... just fair warning...

Edited by zygot

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