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Ahmed Alfadhel

how to get low clocking rate by ARTY 7 ?


Posted (edited)

Hi ,

I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture !

What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?

I read about delays in FPGA , but I found delays are not synthesized in FPGA !

Looking for your help,



Edited by Ahmed Alfadhel

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Posted (edited)

I'm really not too interested in spending a lot of time fixing peoples code or teaching HDLs.. but...

Why did you comment out the enable from your port and make it a local signal? I don't think that you quite understand the concept of enables.

What do you suppose is going on with your concurrent assignment to i_en?

Try to figure out what it is that your code is doing. What's being clocked and what's not? Look at where you assign values to the signal counter ( that's where the answer to your question will be found if your grasp of VHDL for synthesis is sufficient ). Why is counter type integer? What do you supposed happens when the synthesis tool tries to use an unconstrained integer tp implement a counter?

Don't try an stuff all of your logic into one process; put your counter into its own process. Look around for some examples of implementing a counter in VHDL.

My impression is that you haven't quite grasped the basic concepts of the VHDL that you are trying to use.

Here's my suggestion:

Create a standalone LFSR entity, a standalone counter entity, and a toplevel entity that instantiates both the LFSR and counter components.

Don't use type integer anywhere in your code.

Only use if..elsif..else statements in your code.

See if you can shift your LFSR only when the counter reaches a certain value.

Write a testbench to exercise your toplevel source file.

You  may not get exactly what you want at first but you will have a nice little project that along with some help from the simulator can help you learn VHDL.


Edited by zygot

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Posted (edited)
1 hour ago, Ahmed Alfadhel said:

What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?

My my... I'm not sure what LFSR you are using but mine have a shift enable input so that I can use any clock that's available but update the LFSR output at almost any update rate needed. You can create a counter to control the shift enable so that it's synchronous with whatever logic is running at 8 KHz and needs data at that rate.

It's typical in a design to have lots of parts of the logic changing states at lots of different frequencies. You don't want separate clock domains for all of those rates even if those clocks are derived and phase coherent. Sometimes, for high speed applications you do need a higher, phase coherent clock; like in video where there might be a reference clock and a higher but synchronous pixel clock. In general it's best to have the minimum number of clock domains in a design that you can get away with.

FPGA devices don't have long analog or combinatorial delay lines on the order of microseconds or milliseconds. The Series 7 devices do allow adding very small delays to signals coming into FPGA pins via the IDELAY2 primitive. If your device has outputs on pins on an HP bank you can also add similar small delays to output signals using the ODELAY2 primitive. Synchronous delays lines using counters and enables as I mentioned before are the normal way to achieve teh equivalent of the analog delay line that used to be part of some digital logic long long ago.

Edited by zygot

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Posted (edited)

Hi Mr. @zygot,

I added enable signal (i_en) , which is controlled by a counter. As shown in my code below:

-- Library's
library IEEE;
use IEEE.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LFSR3 is
   Port (
      i_clk           : in  std_logic;
      o_lsfr          : out std_logic_vector (2 downto 0)
     -- i_en            : in  std_logic
end LFSR3;

architecture Behavioral of LFSR3 is

signal i_en    : std_logic := '1';
signal r_lfsr	: std_logic_vector(2 downto 0) := "100";
constant maxcount  : integer := 625;
signal counter :  unsigned(9 downto 0) := to_unsigned(0, 10);


  o_lsfr <= r_lfsr;
  LFSR_proc: process(i_clk)
    counter <= (others => '0');
    i_en <= not i_en;
    if (i_en = '1') then
       if(rising_edge(i_clk)) then

          r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
          r_lfsr(1) <= r_lfsr(2);
          r_lfsr(0) <= r_lfsr(1);
       end if;
    -- line 75 (the error)
      freq_8kHz: while (counter <= maxcount) loop
          counter <= counter + 1;
       end loop freq_8kHz;
   end if;     
  end process LFSR_proc;
end Behavioral;

And , when I run synthesize, an error appeared :

"[Synth 8-3380] loop condition does not converge after 2000 iterations ["d:/Users/dell/Vivado_projects/LFSR2/LFSR2.srcs/sources_1/bd/LFSR/ipshared/4f95/src/LFSR3.vhd:75]"
I have pointed to the error location in my code (line 75) . So plz , could you tell me why my loop seems to be infinite (does not converge) !? 


Edited by Ahmed Alfadhel

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