I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture !
What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?
I read about delays in FPGA , but I found delays are not synthesized in FPGA !
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Ahmed Alfadhel
Hi ,
I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture !
What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?
I read about delays in FPGA , but I found delays are not synthesized in FPGA !
Looking for your help,
Thanks
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