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Sami Malik

unable to Transfer more then 32bits from PS to PL through BRAM of Zybo

Question

Hi,

Currently I'm working on a project in which I want to transfer 1MB data from PS to PL using BRAM using custom IP. I receive correct data at PL whenever I send data less then 32 bits from PS to PL  but when I send more bits from PS, I'm unable to receive even a single bit. is there any clock issue as I'm using clock of PS for my custom IP or their is any other problem?

Regards, 

Sami

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Hi @jpeyron,

Yes sure sir. I have attached a screenshot of block design with the code of my custom IP.  And base address of my BRAM is 0x40000000. Similarly I've attached SDK code for transferring data from PS to first four locaiton of BRAM.

Regards,

Sami

Block Design.png

IP Core.txt SDK Code.txt

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Hi @Sami Malik,

When you are trying to send more then 32 bits are you adjusting the addr pin in the multiple_bits and the block memory generator as well as the dout pin on the block memory generator?

best regards,

Jon

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Hi @jpeyron,

Yes i'm updating adress as mentioned in ip core.txt file in previous reply. And I didn't get your point regarding dout. 

I have sent everything regarding my issue. Please help me out sir. 

Regards,

Sami

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Hi @Sami Malik,

We have not altered the BRAM IP core to move more that 32 bits.  Please attach a screen shot of your block design altered to work with more than 32 bits to see what you are altering. In regards to DOUT.  DOUT is the output pin from the Memory generator to the DIN pin on the multiple bits IP Core.

best regards,

Jon

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Hi @jpeyron,

I want to send data in chuncks of 32bits on every positive edge of clock from ps to multiple bits IP Core. so what changes do I have to make in my Bram IP Core or in my code of multiple bits IP or sdk code to do this?

Thanks.

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Hi @Sami Malik,

I reached out to a co-worker about this thread and they pointed out that you are writing into the controllers register space, not the brams memory space.  you are not accessing the 0,1,2,3 addresses of the bram by reading it from rtl based on how you have it set up. They also suggested that you should try to import an example from system.mss to get an idea of how xilinx uses the driver as well.

best regards,

Jon

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