How to replace the function of "adept 2"?

[Allan Flippin]

     I've used the Nexys 3 board for some time and I've found the adept 2 utility to be very useful!  I used the utility to write data to my Nexys 3 board and also read back results to my PC after running some tests.  As long as my FPGA code could access the memories properly, I knew I could transfer results to and from my PC.

     I'm now looking into moving to one of the Artix-based boards.  But Adept doesn't work with them.  I've read the documentation and I don't see any replacement for this capability.  On one of the Arty boards, how does one transfer data with a PC?  I suppose Ethernet could be used but wouldn't that require lots of software?  Perhaps I'm missing some basic concept.  Thanks for any help!

 

Allan

[jpeyron]

Hi @Allan Flippin,

Adept 2 and Adept 2 SDK does work with Artix-7 based FPGA boards. Some of the functionality that was available for older FPGA's in Adept's UI was not done for the newer FPGA.  The Vivado Hardware manager can write to FLASH and can read ILA files. 

The ILA IP Core  which is Vivado's version of chipscope is available at no cost with the free Vivado Webpack edition. Here is a good reference to what is available for each Vivado edition. 

You can also use the USB UART bridge or ethernet to transmit/receive data from a PC using Microblaze or HDL for non-zynq families and the Zynq Processor with Zynq FPGA's. 

I have used the USB UART bridge and serial terminal emulator(tera term) to send/receive data for trouble shooting issues in Artix-7 project development.  

best regards,

Jon

 

[xc6lx45]

Hi,

I think a UART is the least effort. Parsing ASCII hex data in a state machine is easy and intuitive to debug, at the price of 50 % throughput.

If you like, you can have a look at my busbridge3 project here, goes up to 30 MBit/second. The example RTL includes very simple bus logic with a few registers, so it's fairly easy to connect an own design. Note, it's not meant for AXI, microblaze or the like as it occupies the USB end of the JTAG port.

In theory, it should work on any Artix & FTDI board as it doesn't any LOC-constrained pins.

[Allan Flippin]

Jon,

     Thanks for the speedy reply.  Now I'm trying to figure out why I thought Adept 2 wouldn't work on Arty boards.  If indeed it does, my problems are solved.  I'll check the documentation.  If not, I can use a UART as xc6lx45 suggests.  Thanks to you both.

 

Allan

[jpeyron]

Hi @Allan Flippin,

The memory functionality you discuss above for the Nexys 3 is not facilitated for the newer FPGA families like the Artix-7 and ZYNQ.  Adept 2 does still allow users to configure newer xilinx FPGA's using .bit files. 

Adept 2 can be downloaded here along with the Adept 2 reference manual.

best regards,

Jon 

[Allan Flippin]

Jon,

      Yes.  You've hit upon my issue.  The memory read/write functions in the Adept 2 utility were very useful with the Nexys 3.  Does it seem I can still access data through the utility, but I need support in my FPGA code to make the connection to block RAM or whatever I'm using?  Sorry, if I had the board here, I'd just experiment.  But this is going into my decision whether to buy this or a different board for the job.

 

Allan

[jpeyron]

Hi @Allan Flippin,

It's my understanding that there is no current plans on adding access to the memory like for the newer families of FPGA's in Adept 2.  I am also not aware of any other application that facilitates that type of interaction with memory.  

If using the USB UART bridge is a feasible alternative, could you be more specific about your data rate needs for transferring/receiving data to the PC? 

There are quite a few HDL(VHDL/Verilog)  UART Controllers available with a quick google search. We also have projects that transfer data through the USB UART bridge using HDL like the Arty-A7 100T GPIO demo.  

This older tutorial uses the Microblaze processor and uart lite IP Core that uses the USB UART bridge as well.

best regards,

Jon

[Allan Flippin]

Jon,

     I think the USB UART bridge would work for me.  I shouldn't need more than 1Mbaud.  I'd use it to transfer the contents of block RAM to/from PC.  A few seconds to transfer the data seems fine.  As xc6lx45 suggests, it would be a good idea to transfer in Hexscii so I can add a simple command set to control the process.

     Looking at the Arty Z7, I see a different problem.  That board doesn't have an FTDI controller.  I see that instead the board has a TI USB Phy and uses the USB controller embedded in the Zynq 70x0.  In that case, is there any way at all to transfer application data over USB with the PL?  This isn't a show stopper for me.  I don't think I'd benefit much from having ARM CPUs for this application.  Thanks for all your help!

Allan

[jpeyron]

Hi @Allan Flippin,

If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. 

ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor.  

To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. 

Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge.

Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers.

best regards,

Jon

[Allan Flippin]

Jon,

     Thanks.  I'm looking at the information from ftdichip.com.  The only thing I'm unclear about is how the baud rate is set?  I'm trying to find out if my HDL UART block will need auto-baud detect.

Allan

[jpeyron]

Hi @Allan Flippin,

Here is the VHDL code for the UART TX from our GPIO demo for the Arty-A7-100T which sets the tx baud rate to 9600. I have not used auto baud detection since typically we dictate the baud rate in our projects. 

best regards,

Jon