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Issue with zed board simulation and Integrated logic analyzer results


I am using Zed board and having an issue of different results of simulation  and hardware implementation.Results of simulation and hardware implementation are attached.'If' statement is not working properly  identified with red rectangle and value of "spi_enable" signal is not updating marked with green rectangle in the picture attached.

Please guide what is the issue and how can i solve???

Thanks in advance.


Mufasir Fida Qureshi




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Hi @mufasir_qureshi,

Welcome to the Digilent Forums!

Could you attach all of the HDL. Can you be more descriptive about your project. 

best regards,


PS- one of my first verilog SPI controller i missed assigning the signal as an inout. Instead I had assigned it as an input.


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