I'm having a problem with the Arty Z7 HDMI Out demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start). I can build, start and run the demo and it works just fine after a power-cycle, but if I then re-load and re-start the SDK code (via the debugger) without re-loading the FPGA bitstream I get the following error and there is no output from the HDMI port:
Read channel reset failed 11000
VDMA Configuration Initialization failed 1
(error is happening in XAxiVdma_CfgInitialize(), right after XAxiVdma_ChannelInit(RdChannel); and XAxiVdma_ChannelReset(RdChannel);
If I re-load the bitstream before re-launching the code things work fine, but it doesn't seem like I should have to reload the bitstream every time.
Any idea what's going on? I'm using Vivado 2018.3 and version 6.3 (rev 6) of the VDMA IP.
Question
jaypdx
I'm having a problem with the Arty Z7 HDMI Out demo (https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start). I can build, start and run the demo and it works just fine after a power-cycle, but if I then re-load and re-start the SDK code (via the debugger) without re-loading the FPGA bitstream I get the following error and there is no output from the HDMI port:
Read channel reset failed 11000
VDMA Configuration Initialization failed 1
(error is happening in XAxiVdma_CfgInitialize(), right after XAxiVdma_ChannelInit(RdChannel); and XAxiVdma_ChannelReset(RdChannel);
If I re-load the bitstream before re-launching the code things work fine, but it doesn't seem like I should have to reload the bitstream every time.
Any idea what's going on? I'm using Vivado 2018.3 and version 6.3 (rev 6) of the VDMA IP.
Link to comment
Share on other sites
5 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.