Question

I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution.  I know this has sort of been beaten to death...so take it easy on me.  I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up.  I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated.

  • IP block in Vivado is customized as shown in image below.  In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard.
  • Bitstream generates successfully and design is exported to SDK.  I've run numerous applications out of BRAM and DDR3 via the normal microblaze bootloop (i.e. no flash) so I know the system is configured correctly to some degree.  I've tried this both WITH and WITHOUT a compressed bitstream as noted in the tutorial here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start
  • I generated the BSP with xilifs library v5.12 and set 'serial_flash_family' to 5.
  • I then created a user application with a modified linker script to run out of DDR3.  I verified this works just fine in the standard microblaze bootlop as noted above.
  • I generated the 'srec_spi_bootloader' application.  I originally set the memory location to 0x00C00000, but have since used 0x00300000.  Complied the application with no issues.
  • I then generated a bitstream as indicated in the tutorial with the 'srec_spi_bootloader.elf' set to initialize in Block RAM.  
  • Followed the steps for programming flash - first loaded the user application at the memory offset that matches the compiled 'srec_spi_bootloader' application (so 0x00300000).  Then programmed the generated bitstream at offset 0x0.  Originally, I had the wrong memory part selected and have had difficulty finding any documentation that points to the updated part.  Ultimately just read the letters on the actual part itself and found that 's25f128sxxxxxx0-spi-x1_x2_x4' worked.  So that's what I've been using.
  • After programming and power cycling, I see the DONE LED illuminate but nothing happens.  There's been some tweaks to the process here and there, but this seems to be the most convincing order of operations I've been able to find on the web.

As an interesting side note, I can load the flash memory with the application at 0x00300000 and run the 'srec_spi_bootloader' out of the microblaze bootloop when it's set to initialize in Block RAM and it loads the application just fine.  It's just when I add the step of writing the full bitstream to offset 0x0 that it fails to actually run the application on power-up, despite the fact the green DONE LED illuminates.  

Any thoughts????  💡💡💡

Capture1.PNG

Capture2.PNG

Share this post


Link to post
Share on other sites

5 answers to this question

Recommended Posts

  • 0

Hi @vttay03,

I believe that the 0x00C00000 off set will not work since it is a larger FPGA. I will look into this further tomorrow. 

best regards,

Jon

Share this post


Link to post
Share on other sites
  • 0

Any luck?  I tried a few different addresses higher than 0x00C00000 but still not working.  I pulled the datasheet for the SPI flash and it looks like the 128 Mb part has addresses up to 0x00FFFFFF.

Haven't had time to investigate how to calculate the bitstream size to ensure it's not overwriting the stored application once that's loaded into offset 0x0.

Share this post


Link to post
Share on other sites
  • 0

Hi @vttay03,

I have not been able to be able to get the Hello world template to work with the QSPI flash with either the Arty-A7 35T or the Arty-A7-100T in Vivado 2018.3. I will keep looking into this issue with Vivado 2018.3. For now I would suggest using Vivado 2017.4. I was able to complete and verify the Hello world template project into the QSPI flash on the Arty-A7-100 using Vivado 2017.4.  I attached some screen shots of the programming setting in SDK. Also the offset is 0x003D0900 since the HW platform size is the same as the Nexys 4 DDR which has the same FPGA.

best regards,

Jon 

Arty-A7-100-QSPI-2.jpg

Arty-A7-100-QSPI-1.jpg

Share this post


Link to post
Share on other sites
  • 0

Hi @jpeyron--

Just wanted to follow-up and let you know this all worked after rolling back to 2017.4 and using the offset you provided.  Thanks for the help!

Share this post


Link to post
Share on other sites
  • 0

Hi @vttay03, @jpeyron,

I may have a solution to this problem for you. I am working with a Arty A7-100T; and I am designing material that mostly does not make use of a Microblaze / AXI setup.

From a different tutorial, I learned that this board should be configured to operate the boot-up at 33 MHz instead of the default of 3 MHz. Also, the configuration modes should be both JTAG and Master-SPI-x4 selected for the bitstream configuration. By default, a new project in Vivado 2019.1 with the Arty-A7-100 boad selects only configuration of JTAG and no configuration is selected for Flash memory. These options can be found under Open Implemented Design | Tools | Edit Device Properties...

Note that I've noticed that the Arty A7-100T may have a power-on failure where the board only operates correctly if PROG_B is pressed once after adding power by plugging-in USB-A port.

Tim S.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now