Nexys 4 - [drc 23-20] Rule Violation Cfgbvs

[andresaltieri]

Hi everyone,

I have a Nexys4 board and I am trying to generate a simple program in VHDL using Vivado 2014.4 Webpack.

When I get to the Generate Bitstream phase I get the following warning:

-----------------------------

WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

-----------------------

The program apparently works OK even though there is this warning.

I am using the constraints file provided by DIGILENT:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4

where I have uncommented the clock signal, the 7 segment displays and the first switch.

I have tried to solve this but I am new to FPGAs and there is an overwhelming amount of documentation. It would be great if someone could help me. I don't want to change anything and risk damage to the board.

 

I see that the example project provided by Digilent also has the same warnings.

 

Thanks in advance
Andres

 

[hamster]

This link will help you....

 

http://forums.xilinx.com/t5/Design-Entry/Setting-CONFIG-VOLTAGE-and-CFGBVS-using-Vivado-2014-1-GUI/td-p/442462

 

Warnings in FPGA designs are funny things - you may still get plenty of warnings when things are perfectly designed and implemented. You get used to it after a while.

 

When things are not working as expected have a quick look at the warnings before you bother getting out the scope and logic analyser. And once in a when, when you need some time to drink a cup of coffee, have a look over the warnings just to see what is going on in your design - you might just see something that saves an hour or two of debugging.