• 0
Kris Persyn

dvi2rgb issue ( PLLE_ADV)

Question

Hi,

I'm implementing digilent's hdmi-out design on my zybo z7-20. I've already made the pixel logic with the required output signals and error.thumb.PNG.6ed72c58544591ea99845c57eeecceae.PNGproper timing (tested in testbench). However when generating my bitstream, I get this output as an error (see image below called error.PNG). I assume it's because I left SerialClk open (which you should never do)?diagram.thumb.PNG.e751d28f8a460e6903df41133b0d038e.PNGdatasheet.thumb.PNG.c41c566b18a5c260a43ae1bc170f27d3.PNGsrc_clockgen.PNG.504df420e6f6c411faccfa5b6dd2bdb3.PNGio_planning.thumb.PNG.678f415774b2da8b635f383eee8751a9.PNGio_planning.thumb.PNG.678f415774b2da8b635f383eee8751a9.PNG

Share this post


Link to post
Share on other sites

7 answers to this question

Recommended Posts

  • 0

From the IP documentation:

Quote

SerialClk: Optional fast serial clock. Has five times the frequency of PixelClk and are phase-aligned. Can be generated internally.

Optional, if you enable the internal generation option in IP customization. If not, it must be generated external to the IP and provided on the pin.

Share this post


Link to post
Share on other sites
  • 0

Since you took the sources out the packaged IP and instantiated them as a module, please provide the generic parameters you instantiated with.

Share this post


Link to post
Share on other sites
  • 0

Assuming you instantiated with the default generics

kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL";

, you do not have to provide SerialClk to the module.

The error message is complaining about CLKIN1 of the PLL generating SerialClk internally. CLKIN1 is actually PixelClk, so check where it is coming from and if it is a valid signal.

Share this post


Link to post
Share on other sites
  • 0

Hi @elodg,

Agreed. I decided to have it generated internally and the parameters are exactly as shown above. I made the pixelclock with the clock wizard ip. The input is a 200 MHz clock coming from the Zynq 7000 processor. I converted it to 148.5 MHz.

I found the issue though. I forgot to connect CLK to CLKx 🙄... (I run the clock through the timing block to be able to switch between 74.25 and 148.5 in the future). I added this simple line for now..

Let's see if it generates my design this time around. Thanks for helping me look into the right direction.

 

 

clock3.PNG

clock4.PNG

Edited by Kris Persyn

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now