dvi2rgb issue ( PLLE_ADV)

[Kris Persyn]

Hi,

I'm implementing digilent's hdmi-out design on my zybo z7-20. I've already made the pixel logic with the required output signals and proper timing (tested in testbench). However when generating my bitstream, I get this output as an error (see image below called error.PNG). I assume it's because I left SerialClk open (which you should never do)?

[elodg]

From the IP documentation:

Quote

SerialClk: Optional fast serial clock. Has five times the frequency of PixelClk and are phase-aligned. Can be generated internally.

Optional, if you enable the internal generation option in IP customization. If not, it must be generated external to the IP and provided on the pin.

[elodg]

Since you took the sources out the packaged IP and instantiated them as a module, please provide the generic parameters you instantiated with.

[elodg]

Assuming you instantiated with the default generics

kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL";

, you do not have to provide SerialClk to the module.

The error message is complaining about CLKIN1 of the PLL generating SerialClk internally. CLKIN1 is actually PixelClk, so check where it is coming from and if it is a valid signal.

[Kris Persyn]

Hi @elodg,

Agreed. I decided to have it generated internally and the parameters are exactly as shown above. I made the pixelclock with the clock wizard ip. The input is a 200 MHz clock coming from the Zynq 7000 processor. I converted it to 148.5 MHz.

I found the issue though. I forgot to connect CLK to CLKx ?... (I run the clock through the timing block to be able to switch between 74.25 and 148.5 in the future). I added this simple line for now..

Let's see if it generates my design this time around. Thanks for helping me look into the right direction.

 

 

[Kris Persyn]

Hi @elodg,

Now I'm getting this error. I think I've configured the clocking wizard wrongly?

[Kris Persyn]

I was able to solve it by selecting 'global' when generating output products. Other solutions are mentioned here (https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-REQP-1712-Input-clock-driver/td-p/586641)

[jpeyron]

Hi @Kris Persyn,

Glad to hear you were able to resolve the issue. Thank you for sharing what you had to do.

best regards,

Jon