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VIVADO: Partial Reconfiguration



I have been trying to implement Partial Reconfiguration of AES on Zedboard. I wanted to ask if i have netlist with me, can i use that netlist as one of my Partially reconfigured module? My second question is that if i create a block design having AXI interconnect, my IP and Processor, is it possible that i only declare my own IP as partially reconfigurable module?

Any help would be highly appreciated. Thank you

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Hi @Hunaina,

We have not worked with partially reconfiguration.

Unfortunately,  we would not be much help with this topic. Hopefully one of the more experienced community members will have some input for you. 

I would also reach out to Xilinx support as well.

best regards,


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