spikes on script plot

[ramestica]

Hi,

in the attached snapshot the 8 bits bus runs at a frequency of 2 MHz (from 0 up to 255). The bus row shows it in decimal format. The script simply plots the bus data. For a moment I thought that the spikes on the plot were some artifact on the actual signal I'm generating. But after checking, I could not find anything wrong. And now I realize that decimal values in the Bus row do not show any spike.

I suppose that the problem is that triggering on bit7 captures the other 7 bits a bit too soon some times. How could I improve this? And why is that decimal Bus values do not show exactly what the script is plotting?

Thanks,

Rodrigo

 

 

[ramestica]

sorry, it was just a matter of zooming in to confirm what's happening, see attached snapshot.

My question is then how to delay the capture of all bits after the trigger? Or is it more sensible to assume that I should provide yet another signal that switches (use as trigger) when all bits are for sure stable?

[attila]

Hi @ramestica

The glitches you are seeing are due to the different propagation delay of simultaneously switching signals and the jitter between the generator and capture devices.
Make sure to have ground connection between the generator and capture device. Without common ground the devices can be damaged or signals seen wrongly.

You can use an additional clock signal and sample based on this.

Here with AD2, next to the counter on DIO8 a clock is generated which rising edge is at 180* relative to the counter toggle:

These AD2 DIO signals are connected to the DD DIN lines.

The DD is configured to perform Sync capture on having clock on DIN8.
Make the Bus row taller to can see the analog representation.

[ramestica]

@attila, many thanks for the confirmation that a clocking signal to synchronize the trigger is the way to go. I really appreciate your time setting up the experiment to show-and-tell with detail.

I have also realized now that the Bus configuration itself allows for a clock definition, which is what I will be trying soon.

Last but not least, making the bus taller is quite a significative realization! This posting ended up being two times useful to me.

Rodrigo

 

 

 

 

[attila]

Hi @ramestica

Yes, you can also define clock for the bus interpreter.