I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get.
The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems.
The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0].
1. I added in the additional input - input [1:0] sw
2. I added in the case statement (which is currently commented out)
3. I commented out the original assignment of led - //assign led = clkdiv[26];
The problem crops up immediately with a Verilog error showing on the following line: case(sw)
- The error states: Error: 'sw' is not a constant
I've spent hours trying various changes...all to no avail.
genvar i;
generate
for (i = 1; i < 27; i=i+1)
begin : dff_gen_label
dff dff_inst (
.clk(clkdiv[i-1]),
.rst(rst),
.D(din),
.Q(clkdiv)
);
end
endgenerate
assign din = ~clkdiv;
/*
begin
case(sw)
2'b00: assign led = clkdiv[26];
2'b01: assign led = clkdiv[25];
2'b10: assign led = clkdiv[24];
2'b11: assign led = clkdiv[23];
default: assign led = clkdiv[26];
endcase
end
*/
Question
jrosengarden
Hi All:
I'm fairly new to both Verilog and the Basys3 board. I'm working thru a 'self education' course. I'm having a problem with the following module. I could use any answers/advice I can get.
The module, as posted (below) is processed by Vivado properly, loads into the Basys3 board and runs as expected with the LED blinking at a frequency of .7451 Hz. No problems.
The example I'm working thru then threw out a 'challenge' of changing the frequency of the blinking LED based on the positions of two switches [1:0].
1. I added in the additional input - input [1:0] sw
2. I added in the case statement (which is currently commented out)
3. I commented out the original assignment of led - //assign led = clkdiv[26];
The problem crops up immediately with a Verilog error showing on the following line: case(sw)
- The error states: Error: 'sw' is not a constant
I've spent hours trying various changes...all to no avail.
HELP....PLEASE!!!! Thanks Tons!
VERILOG MODULE:
module clk_divider(
input clk,
input rst,
input [1:0] sw,
output led
);
wire [26:0] din;
wire [26:0] clkdiv;
dff dff_inst (
.clk(clk),
.rst(rst),
.D(din[0]),
.Q(clkdiv[0])
);
genvar i;
generate
for (i = 1; i < 27; i=i+1)
begin : dff_gen_label
dff dff_inst (
.clk(clkdiv[i-1]),
.rst(rst),
.D(din),
.Q(clkdiv)
);
end
endgenerate
assign din = ~clkdiv;
/*
begin
case(sw)
2'b00: assign led = clkdiv[26];
2'b01: assign led = clkdiv[25];
2'b10: assign led = clkdiv[24];
2'b11: assign led = clkdiv[23];
default: assign led = clkdiv[26];
endcase
end
*/
assign led = clkdiv[26];
endmodule
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