Fundimental FPGA question

[RelativeHardware]

Hello everyone.

Recently I bought the Pmod i2s2: stereo Audio Input and Output module. I got this working with the example project. As part of the exercise I even translated the I2S part from Verilog to VHDL, and it’s working great by tying the output AXIS directly to the input (without the volume control part).

digilent pmod i2s2 code

My own vhdl equivalent

What I’m a bit confused about, and this may be my limited knowledge of FPGA’s, is that everything is handled on the rising edge of the clock. For example in the digilent pmod i2s2 code in line 135 and 136 the rx_data_l and r register are written on the posedge of the axis_clk. So eventually you get the waveform as in the picture.

So far I understand this principle clearly. What I don’t get is why this data on the receive side of the axi is read in on the posedge of the axis_clk. In line 83 and 85 the input data of the axis is written to tx_data_r and l. How can this happen correctly, doesn’t the data bus need some time to change the values. Now it seems that the data is written and read at exactly the same time.

Now I want to extend this project by writing the samples into blockram and have the same issue. Can you write the address and data on the same clock as the blockram writes the data, or is it better to write the data on the falling edge for example.

[zygot]

6 hours ago, RelativeHardware said:

Now it seems that the data is written and read at exactly the same time

So you already understand the 'prime directive' of FPGA design, that is ask "Why...", even if the question seems to be silly. Your question is basic but not silly.  Welcome to digital logic design. You are correct that it takes time for data to change values. This is true for clocked data or combinatorial data. There are also delays for both clock and data signals to propagate along wires outside the FPGA device and from one area of the FPGA to another area. Sometimes the logic at the sink end of a signal will be clocked by the same edge as the source end... often it will be clocked by a later ( in time ) edge. If you have a wide clocked bus of signals it is possible for some of the signals to be clocked at different edges than the others.Sometimes it doesn't matter which edge but often it matters a lot. To further complicate matters your clock edges are not exactly one clock period apart due to jitter and drift. And then delays are temperature dependent. What's important for clocked logic are setup and hold times relative to the clock edge when logic clocks a signal. It doesn't matter if the signal was created by a clock or combinatorial logic. Things get really tricky when you have multiple clocks and want to pass information between these clock domains. If the clocks are unrelated ( that is one was not derived from the other and has a relatively fixed phase relationship ) things get even more tricky.

You can read about AC switching characteristics for the FPGA on your board in the datasheet. Even if you don't understand all of the parameters this is good reading for all FPGA developers.

You need to have a reasonable grasp of the fundamental concepts of digital design if you want to have success with and HDL. It is quite possible to have fun with only the most basic concepts in mind as you develop skill with your HDL but as your designs get more complicated your understanding of digital logic design will have to grow as well. There is no arriving at a destination, just asking questions and gaining knowledge and insight and hopefully skill.