• 0
Sduru

AXI4 and Vivado ILA

Question

Hello,

My question is related to AXI4 usage in digital image processing. As I am new in image processing with HDL coding, I need to get this valuable answer from you @jpeyron @zygot @JColvin especially. I am using Zybo Z7 and PCAM 5C for my project. As a good start in my opinion, I wanna get digital image from CMOS through D-PHY and MIPI CSI-2 RX. And then, I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design? In other words, can I pass the data from CSI-2 interface to ILA directly? If it is possible only with AXI interface, so I will deeply study the AXI4 referance manuals.  Many thanks...

Share this post


Link to post
Share on other sites

14 answers to this question

Recommended Posts

  • 0
6 hours ago, Sduru said:

I just wanna scope the digital image bits by using Integrated Logic Analyzer (ILA). For this purpose, do I have to use AXI4 streaming and/or other AXI IPs in my VHDL design?

No, you should be able to use any of the PL input pins for your own logic or and ILA. You might have to create copies of output signals.

Share this post


Link to post
Share on other sites
  • 0

Thank you @zygot . I've created the block design without AXI4 Stream like in the following:

image.png.df545384c90f8b84da2b5899f353e2e9.png

 

But, I am getting the following errors:

[Common 17-55] 'get_property' expects at least one object. Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object.

[BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-55] 'get_property' expects at least one object. ::digilentinc.com_ip_MIPI_D_PHY_RX_1.3::post_propagate Line 6

Do you have any idea for those errors above?

 

Share this post


Link to post
Share on other sites
  • 0

In the link https://www.xilinx.com/support/answers/56169.html , it says that this error is related to XDC file. 

"The following are some common causes of this issue. XDC constraints are case sensitive. These warnings can occur if the case type of the object name in XDC is not the same as the signal in the RTL code"

But in my constraints file, there is no case sensitive problem. I cannot solve the problem. Please help...

Share this post


Link to post
Share on other sites
  • 0
Posted (edited)

In my experience this message generally does refer to the tools not being able to relate constraint names to source signal names. I don't use the board design flow quite the same way as you do. I get Vivado to create an HDL for the board design schematic. It's very important to make sure that your manage this file rather than use the default setting of Vivado managing the file. I then create a toplevel file that instantiates this HDL and also all of my one code. This is also where I would put my ILA.

You need to understand that when you use Xilinx IP Vivado usually creates constraints files for that IP but you won't see it listed in the GUI. You have to go though the IP directory and look for it (them). Sometimes you can wade through all of the messages and find the source of the problem but not always. In my experience the more you let Vivado manage stuff the less informed you will be by what exactly Vivado is doing... so I've learned to restrict Vivado to the extent possible. It's a little more effort for me up front but much easier to resolve problems.

Just before I was about to submit this I looked over your block diagram again. Are you sure that all of it wasn't optimized out since you are no longer connecting the MIPI interface to the PS? Try my approach and start over with the full working board design. Your toplevel source should be an HDL of your choice and you can tap off the input signals to connect to your ILA.

An alternate approach would be to cut out the PS altogether and just do everything in your HDL. This might get messy as you'll have to make Vivado think that all of your output signals are being used.

Edited by zygot

Share this post


Link to post
Share on other sites
  • 0
Posted (edited)

Thanks for your reply @zygot . As you said about the problem, I've checked the constraints names. I am using Zybo Z7 board and its constraints file in the link https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc . I realised that some of the port names of MIPI D-PHY IP are different from those in the constraints file. I've corrected all of them and toggled non-used pins like in the following:

image.thumb.png.d27bb7f44c814647f1bbd55cdab55870.png

However, I am still getting the same errors. I will be very appreciated if we solve this problem... Many thanks... 

Edited by Sduru

Share this post


Link to post
Share on other sites
  • 0

Hi @Sduru,

Make sure you are using the Vivado library from this branch in GitHub.  Do you have the Digilent Board files installed correctly.

Please attach a screen shot of the errors you are getting in Vivado.

As well as a screen shot of your current block design along with wrapper and xdc file.

best regards,

Jon

 

Share this post


Link to post
Share on other sites
  • 0
Posted (edited)

Hello Dear @jpeyron

  • I have updated the Vivado library from the link you provided. Now, I am using the latest versions MIPI_D_PHY_RX_1 and MIPI_CSI_2_RX_1. 
  • I double checked that I've installed Digilent board files. I see it with the correct name as Zybo Z7-20 (xc7z020clg400-1) in my project summary.
  • You can see my block design like in the attachment. (My simple aim is just to see digital image data in the output of MIPI CSI-2 captured from PCAM OV5640 CMOS).
  • You can also see my constraints file in the attachment. I am just using that from the git hub link here
  • At the end, I am getting the same errors attached when I validate it.  

Maybe I am doing a simple mistake related to connections and/or clocking / resetting etc. but I don't know. 

Cheers,

Sami 

 

Block_design.png

Constraints.png

 

Errors.png

Edited by Sduru

Share this post


Link to post
Share on other sites
  • 0

Hi @Sduru<

I believe that these errors are due to differences between the xdc and wrapper file. 

Please attach the xdc and wrapper file from your project. Also case matters so make sure that all of the constraints in the wrapper and the xdc match as well as comment out any constraints in the xdc that you are not using in the wrapper file.

best regards,

Jon

Share this post


Link to post
Share on other sites
  • 0

Hi Dear @jpeyron

Please find the xdc and wrapper files from my project. I have corrected some of the port names in the xdc file and matched with the wrapper port names but still getting the same errors. 

From my observation, there is no any definition in the xdc file for the m_axis_video port from CSI-2 to ILA. Do you think that it maybe the reason?

Many thanks..

Sami

Wrapper.txt Constraints.txt

Share this post


Link to post
Share on other sites
  • 0

Hello All @jpeyron @JColvin ,

Do I have to include all the ports definitions of the wrapper in the Constraints file? For example,  there are some ports (resets, sys_clock etc.) which are not in the constraints like 

    m_axis_video_0_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 );
    m_axis_video_0_tlast : out STD_LOGIC;
    m_axis_video_0_tready : in STD_LOGIC;
    m_axis_video_0_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_video_0_tvalid : out STD_LOGIC;
    reset_rtl : in STD_LOGIC;
    reset_rtl_0 : in STD_LOGIC;
    sys_clock : in STD_LOGIC

Could it be the reason? 

Regards

Sami

Share this post


Link to post
Share on other sites
  • 0
Posted (edited)

Hi @jpeyron

I've made S_AXI_Lite input as 'external', and then solved the problem. Now, there is no any constraints issue at the moment, and the validation is OK that screenshot is attached.

After the successful validation of my project, I started to synthesize it. But, at this time, I've got the error 'Submodule Runs Failed' . The error screen is attached. The error log:

ERROR: [Synth 8-439] module 'design_1_MIPI_CSI_2_RX_1_0' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 485.297 ; gain = 153.523
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
5 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed May  8 13:18:21 2019...
 

There is an explanation in the Xilinx link here . I've followed the steps, but I am not able to synthesize it.

As a result, I still couldn't finish my project, and cannot see my PCAM digital signals on ILA...

Cheers,

SamiValidation_OK.thumb.png.217e2a0bd1f3a40f4b600e704de6de09.pngSynth_error.thumb.png.b26f8e8f54d79e8a24908e07e23ebc8d.png

Edited by Sduru

Share this post


Link to post
Share on other sites
  • 0
On 5/9/2019 at 11:48 PM, jpeyron said:

Hi @Sduru,

Here and here are forum threads that should be helpful with fixing the IP error you are experiencing.

best regards,

Jon

Hello Jon,

Thanks for your reply. The problem has been solved. 

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now