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Anusha Kodimela

DCM Fails to work after programming bit file to the board

Question

Board:Nexys2 Spartan 3E

I have used a DCM Core gen to convert the system clock 50MHz to 200 Mhz and added the component to my design,port mapped signals  as below not used locked and rest pins while generating the coregen..

CLKIN_IN => Clock,  ----input 50 Mhz clock 
        CLKFX_OUT => clk,---output 200Mhz clock
        CLKIN_IBUFG_OUT => open,
        CLK0_OUT => open

the clk signal (output from dcm)is being used now in my design instead of Clock(50 Mhz.I am displaying a count value on a seven segment display which has worked before using dcm (for 50 Mhz clock).I have not seen any error or warnings after implementing the DCM .The simulation seems working as expected.But I am not seeing the output which I have to see in the board after programming it.

Did I forget implementing any other step?My ucf looks like below and  If I insert the first lines of the ucf I am getting a timing constraint waning for dcm constraints file.Kindly help.

# Clock
#NET "Clock" TNM_NET = "clk_ref";
#TIMESPEC "TS_clk" =PERIOD: "clk_ref": 20ns:PRIORITY 1; #HIGH 50 %;            
# 50MHz


NET "Clock"                     LOC="B8" | IOSTANDARD="LVCMOS33";#50MHz Clock Input
NET "Counter_enable"       LOC="L15" | IOSTANDARD="LVCMOS33";#L15-JA1 
NET "Counter_disable"       LOC="K12" | IOSTANDARD="LVCMOS33";#K12-JA2  
NET "Anode_Activate<0>"  LOC="F17" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<1>"  LOC="H17" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<2>"  LOC="C18" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<3>"  LOC="F15" | IOSTANDARD="LVCMOS33";
NET "LED_out<6>"  LOC="L18" | IOSTANDARD="LVCMOS33";
NET "LED_out<5>"  LOC="F18" | IOSTANDARD="LVCMOS33";
NET "LED_out<4>"  LOC="D17" | IOSTANDARD="LVCMOS33";
NET "LED_out<3>"  LOC="D16" | IOSTANDARD="LVCMOS33";
NET "LED_out<2>"  LOC="G14" | IOSTANDARD="LVCMOS33";
NET "LED_out<1>"  LOC="J17" | IOSTANDARD="LVCMOS33";
NET "LED_out<0>"  LOC="H14" | IOSTANDARD="LVCMOS33";

 

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Hi @Anusha Kodimela,

Here is the Nexys 2 resource center which has tutorials and example demo's. 

Here is the Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs xilinx XAPP462. Here is a non-digilent tutorial for using the DCM. Here is the Xilinx DCM web page.

Please attach a screen shot of the errors you are getting when you un-comment the clock portion of the ucf and your HDL(verilog/VHDL) top file.

best regards,

Jon

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Release 14.7 Trace (nt64)

Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

 

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4

-n 3 -fastpaths -xml CounterDesign_withFIFO_DCM.twx

CounterDesign_withFIFO_DCM.ncd -o CounterDesign_withFIFO_DCM.twr

CounterDesign_withFIFO_DCM.pcf -ucf CounterDesign_withFIFO_DCM_ucf.ucf

 

Design file: CounterDesign_withFIFO_DCM.ncd

Physical constraint file: CounterDesign_withFIFO_DCM.pcf

Device,package,speed: xc3s1200e,fg320,-4 (PRODUCTION 1.27 2013-10-13)

Report level: verbose report

 

Environment Variable Effect

-------------------- ------

NONE No environment variables were set

--------------------------------------------------------------------------------

 

 

INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

option. All paths that are not constrained will be reported in the

unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

a 50 Ohm transmission line loading model. For the details of this model,

and for more information on accounting for different loading conditions,

please see the device datasheet.

INFO:Timing:3390 - This architecture does not support a default System Jitter

value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock

Uncertainty calculation.

INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and

'Phase Error' calculations, these terms will be zero in the Clock

Uncertainty calculation. Please make appropriate modification to

SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase

Error.

 

================================================================================

Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%;

For more information, see Period Analysis in the Timing Closure User Guide (UG612).

0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints

0 timing errors detected. (0 component switching limit errors)

Minimum period is 6.000ns.

--------------------------------------------------------------------------------

 

Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH 50%;

--------------------------------------------------------------------------------

Slack: 1.933ns (period - min period limit)

Period: 5.000ns

Min period limit: 3.067ns (326.052MHz) (Tdcmpfx)

Physical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKFX

Logical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKFX

Location pin: DCM_X1Y3.CLKFX

Clock network: Inst_DCM_200Mhz/CLKFX_BUF

--------------------------------------------------------------------------------

Slack: 14.000ns (period - (min low pulse limit / (low pulse / period)))

Period: 20.000ns

Low pulse: 10.000ns

Low pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)

Physical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKIN

Logical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKIN

Location pin: DCM_X1Y3.CLKIN

Clock network: Inst_DCM_200Mhz/CLKIN_IBUFG

--------------------------------------------------------------------------------

Slack: 14.000ns (period - (min high pulse limit / (high pulse / period)))

Period: 20.000ns

High pulse: 10.000ns

High pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)

Physical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKIN

Logical resource: Inst_DCM_200Mhz/DCM_SP_INST/CLKIN

Location pin: DCM_X1Y3.CLKIN

Clock network: Inst_DCM_200Mhz/CLKIN_IBUFG

--------------------------------------------------------------------------------

 

================================================================================

Timing constraint: TS_Inst_DCM_200Mhz_CLKFX_BUF = PERIOD TIMEGRP "Inst_DCM_200Mhz_CLKFX_BUF" TS_clk / 4 HIGH 50%;

For more information, see Period Analysis in the Timing Closure User Guide (UG612).

946 paths analyzed, 74 endpoints analyzed, 18 failing endpoints

18 timing errors detected. (18 setup errors, 0 hold errors, 0 component switching limit errors)

Minimum period is 6.427ns.

--------------------------------------------------------------------------------

 

Paths for end point count_5 (SLICE_X76Y72.CE), 33 paths

--------------------------------------------------------------------------------

Slack (setup path): -1.427ns (requirement - (data path - clock path skew + uncertainty))

Source: count_7 (FF)

Destination: count_5 (FF)

Requirement: 5.000ns

Data Path Delay: 6.416ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_7 to count_5

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X79Y72.XQ Tcko 0.591 count<7>

count_7

SLICE_X79Y74.G2 net (fanout=3) 1.011 count<7>

SLICE_X79Y74.COUT Topcyg 1.001 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<1>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_5

------------------------------------------------- ---------------------------

Total 6.416ns (3.417ns logic, 2.999ns route)

(53.3% logic, 46.7% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.415ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_5 (FF)

Requirement: 5.000ns

Data Path Delay: 6.404ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_5

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X76Y74.F4 net (fanout=4) 0.942 count<3>

SLICE_X76Y74.X Tilo 0.759 count_not000224

count_not000224

SLICE_X78Y74.F3 net (fanout=1) 0.349 count_not000224

SLICE_X78Y74.X Tilo 0.759 N6

count_not000243_SW0

SLICE_X78Y75.F1 net (fanout=1) 0.119 N6

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_5

------------------------------------------------- ---------------------------

Total 6.404ns (3.817ns logic, 2.587ns route)

(59.6% logic, 40.4% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.317ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_5 (FF)

Requirement: 5.000ns

Data Path Delay: 6.306ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_5

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X79Y74.F4 net (fanout=4) 0.739 count<3>

SLICE_X79Y74.COUT Topcyf 1.162 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<0>

Mcompar_max_ticks_cmp_lt0000_cy<0>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_5

------------------------------------------------- ---------------------------

Total 6.306ns (3.579ns logic, 2.727ns route)

(56.8% logic, 43.2% route)

 

--------------------------------------------------------------------------------

 

Paths for end point count_4 (SLICE_X76Y72.CE), 33 paths

--------------------------------------------------------------------------------

Slack (setup path): -1.427ns (requirement - (data path - clock path skew + uncertainty))

Source: count_7 (FF)

Destination: count_4 (FF)

Requirement: 5.000ns

Data Path Delay: 6.416ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_7 to count_4

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X79Y72.XQ Tcko 0.591 count<7>

count_7

SLICE_X79Y74.G2 net (fanout=3) 1.011 count<7>

SLICE_X79Y74.COUT Topcyg 1.001 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<1>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_4

------------------------------------------------- ---------------------------

Total 6.416ns (3.417ns logic, 2.999ns route)

(53.3% logic, 46.7% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.415ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_4 (FF)

Requirement: 5.000ns

Data Path Delay: 6.404ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_4

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X76Y74.F4 net (fanout=4) 0.942 count<3>

SLICE_X76Y74.X Tilo 0.759 count_not000224

count_not000224

SLICE_X78Y74.F3 net (fanout=1) 0.349 count_not000224

SLICE_X78Y74.X Tilo 0.759 N6

count_not000243_SW0

SLICE_X78Y75.F1 net (fanout=1) 0.119 N6

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_4

------------------------------------------------- ---------------------------

Total 6.404ns (3.817ns logic, 2.587ns route)

(59.6% logic, 40.4% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.317ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_4 (FF)

Requirement: 5.000ns

Data Path Delay: 6.306ns (Levels of Logic = 3)

Clock Path Skew: -0.011ns (0.082 - 0.093)

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_4

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X79Y74.F4 net (fanout=4) 0.739 count<3>

SLICE_X79Y74.COUT Topcyf 1.162 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<0>

Mcompar_max_ticks_cmp_lt0000_cy<0>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X76Y72.CE net (fanout=8) 1.177 count_not0002

SLICE_X76Y72.CLK Tceck 0.555 count<5>

count_4

------------------------------------------------- ---------------------------

Total 6.306ns (3.579ns logic, 2.727ns route)

(56.8% logic, 43.2% route)

 

--------------------------------------------------------------------------------

 

Paths for end point count_3 (SLICE_X78Y73.CE), 33 paths

--------------------------------------------------------------------------------

Slack (setup path): -1.396ns (requirement - (data path - clock path skew + uncertainty))

Source: count_7 (FF)

Destination: count_3 (FF)

Requirement: 5.000ns

Data Path Delay: 6.396ns (Levels of Logic = 3)

Clock Path Skew: 0.000ns

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_7 to count_3

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X79Y72.XQ Tcko 0.591 count<7>

count_7

SLICE_X79Y74.G2 net (fanout=3) 1.011 count<7>

SLICE_X79Y74.COUT Topcyg 1.001 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<1>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X78Y73.CE net (fanout=8) 1.157 count_not0002

SLICE_X78Y73.CLK Tceck 0.555 count<3>

count_3

------------------------------------------------- ---------------------------

Total 6.396ns (3.417ns logic, 2.979ns route)

(53.4% logic, 46.6% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.384ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_3 (FF)

Requirement: 5.000ns

Data Path Delay: 6.384ns (Levels of Logic = 3)

Clock Path Skew: 0.000ns

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_3

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X76Y74.F4 net (fanout=4) 0.942 count<3>

SLICE_X76Y74.X Tilo 0.759 count_not000224

count_not000224

SLICE_X78Y74.F3 net (fanout=1) 0.349 count_not000224

SLICE_X78Y74.X Tilo 0.759 N6

count_not000243_SW0

SLICE_X78Y75.F1 net (fanout=1) 0.119 N6

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X78Y73.CE net (fanout=8) 1.157 count_not0002

SLICE_X78Y73.CLK Tceck 0.555 count<3>

count_3

------------------------------------------------- ---------------------------

Total 6.384ns (3.817ns logic, 2.567ns route)

(59.8% logic, 40.2% route)

 

--------------------------------------------------------------------------------

Slack (setup path): -1.286ns (requirement - (data path - clock path skew + uncertainty))

Source: count_3 (FF)

Destination: count_3 (FF)

Requirement: 5.000ns

Data Path Delay: 6.286ns (Levels of Logic = 3)

Clock Path Skew: 0.000ns

Source Clock: clk rising at 0.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Maximum Data Path: count_3 to count_3

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.592 count<3>

count_3

SLICE_X79Y74.F4 net (fanout=4) 0.739 count<3>

SLICE_X79Y74.COUT Topcyf 1.162 Mcompar_max_ticks_cmp_lt0000_cy<1>

Mcompar_max_ticks_cmp_lt0000_lut<0>

Mcompar_max_ticks_cmp_lt0000_cy<0>

Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.CIN net (fanout=1) 0.000 Mcompar_max_ticks_cmp_lt0000_cy<1>

SLICE_X79Y75.COUT Tbyp 0.118 Mcompar_max_ticks_cmp_lt0000_lut<3>

Mcompar_max_ticks_cmp_lt0000_cy<2>

Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.F4 net (fanout=17) 0.811 Mcompar_max_ticks_cmp_lt0000_cy<3>

SLICE_X78Y75.X Tif5x 1.152 count_not0002

count_not0002811

count_not000281_f5

SLICE_X78Y73.CE net (fanout=8) 1.157 count_not0002

SLICE_X78Y73.CLK Tceck 0.555 count<3>

count_3

------------------------------------------------- ---------------------------

Total 6.286ns (3.579ns logic, 2.707ns route)

(56.9% logic, 43.1% route)

 

--------------------------------------------------------------------------------

 

Hold Paths: TS_Inst_DCM_200Mhz_CLKFX_BUF = PERIOD TIMEGRP "Inst_DCM_200Mhz_CLKFX_BUF"

TS_clk / 4 HIGH 50%;

--------------------------------------------------------------------------------

 

Paths for end point Counterout_3 (SLICE_X78Y81.BX), 1 path

--------------------------------------------------------------------------------

Slack (hold path): 1.405ns (requirement - (clock path skew + uncertainty - data path))

Source: count_3 (FF)

Destination: Counterout_3 (FF)

Requirement: 0.000ns

Data Path Delay: 1.408ns (Levels of Logic = 0)

Clock Path Skew: 0.003ns (0.096 - 0.093)

Source Clock: clk rising at 5.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Minimum Data Path: count_3 to Counterout_3

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y73.XQ Tcko 0.474 count<3>

count_3

SLICE_X78Y81.BX net (fanout=4) 0.800 count<3>

SLICE_X78Y81.CLK Tckdi (-Th) -0.134 Counterout<3>

Counterout_3

------------------------------------------------- ---------------------------

Total 1.408ns (0.608ns logic, 0.800ns route)

(43.2% logic, 56.8% route)

 

--------------------------------------------------------------------------------

 

Paths for end point count_1 (SLICE_X79Y73.F4), 1 path

--------------------------------------------------------------------------------

Slack (hold path): 1.483ns (requirement - (clock path skew + uncertainty - data path))

Source: cebuffer (FF)

Destination: count_1 (FF)

Requirement: 0.000ns

Data Path Delay: 1.479ns (Levels of Logic = 1)

Clock Path Skew: -0.004ns (0.005 - 0.009)

Source Clock: clk rising at 5.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Minimum Data Path: cebuffer to count_1

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y70.YQ Tcko 0.522 cebuffer

cebuffer

SLICE_X79Y73.F4 net (fanout=20) 0.441 cebuffer

SLICE_X79Y73.CLK Tckf (-Th) -0.516 count<1>

count_mux0000<1>1

count_1

------------------------------------------------- ---------------------------

Total 1.479ns (1.038ns logic, 0.441ns route)

(70.2% logic, 29.8% route)

 

--------------------------------------------------------------------------------

 

Paths for end point count_7 (SLICE_X79Y72.F4), 1 path

--------------------------------------------------------------------------------

Slack (hold path): 1.483ns (requirement - (clock path skew + uncertainty - data path))

Source: cebuffer (FF)

Destination: count_7 (FF)

Requirement: 0.000ns

Data Path Delay: 1.479ns (Levels of Logic = 1)

Clock Path Skew: -0.004ns (0.005 - 0.009)

Source Clock: clk rising at 5.000ns

Destination Clock: clk rising at 5.000ns

Clock Uncertainty: 0.000ns

 

Minimum Data Path: cebuffer to count_7

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

SLICE_X78Y70.YQ Tcko 0.522 cebuffer

cebuffer

SLICE_X79Y72.F4 net (fanout=20) 0.441 cebuffer

SLICE_X79Y72.CLK Tckf (-Th) -0.516 count<7>

count_mux0000<7>1

count_7

------------------------------------------------- ---------------------------

Total 1.479ns (1.038ns logic, 0.441ns route)

(70.2% logic, 29.8% route)

 

--------------------------------------------------------------------------------

 

Component Switching Limit Checks: TS_Inst_DCM_200Mhz_CLKFX_BUF = PERIOD TIMEGRP "Inst_DCM_200Mhz_CLKFX_BUF"

TS_clk / 4 HIGH 50%;

--------------------------------------------------------------------------------

Slack: 3.348ns (period - (min low pulse limit / (low pulse / period)))

Period: 5.000ns

Low pulse: 2.500ns

Low pulse limit: 0.826ns (Tcl)

Physical resource: count<3>/CLK

Logical resource: count_3/CK

Location pin: SLICE_X78Y73.CLK

Clock network: clk

--------------------------------------------------------------------------------

Slack: 3.348ns (period - (min high pulse limit / (high pulse / period)))

Period: 5.000ns

High pulse: 2.500ns

High pulse limit: 0.826ns (Tch)

Physical resource: count<3>/CLK

Logical resource: count_3/CK

Location pin: SLICE_X78Y73.CLK

Clock network: clk

--------------------------------------------------------------------------------

Slack: 3.348ns (period - min period limit)

Period: 5.000ns

Min period limit: 1.652ns (605.327MHz) (Tcp)

Physical resource: count<3>/CLK

Logical resource: count_3/CK

Location pin: SLICE_X78Y73.CLK

Clock network: clk

--------------------------------------------------------------------------------

 

 

Derived Constraint Report

Derived Constraints for TS_clk

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

| | Period | Actual Period | Timing Errors | Paths Analyzed |

| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk | 20.000ns| 6.000ns| 25.708ns| 0| 18| 0| 946|

| TS_Inst_DCM_200Mhz_CLKFX_BUF | 5.000ns| 6.427ns| N/A| 18| 0| 946| 0|

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

 

1 constraint not met.

 

 

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

 

Clock to Setup on destination clock Clock

---------------+---------+---------+---------+---------+

| Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

Clock | 6.427| | | |

---------------+---------+---------+---------+---------+

 

 

Timing summary:

---------------

 

Timing errors: 18 Score: 16949 (Setup/Max: 16949, Hold: 0)

 

Constraints cover 946 paths, 0 nets, and 140 connections

 

Design statistics:

Minimum period: 6.427ns{1} (Maximum frequency: 155.594MHz)

 

 

------------------------------------Footnotes-----------------------------------

1) The minimum period statistic assumes all single cycle delays.

 

Analysis completed Tue Apr 09 13:24:17 2019

--------------------------------------------------------------------------------

 

Trace Settings:

-------------------------

Trace Settings

 

Peak Memory Usage: 177 MB


 

 

image.png

CounterDesign_withoutFIFO_DCM.vhd

Edited by JColvin
added spoiler for visual compactness

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Hi @Anusha Kodimela,

1) Can you attach screen shots of your DCM wizard selections. 

2) Is the DCM wizard creating the clocking part of the UCF text shown below? 

# Clock
#NET "Clock" TNM_NET = "clk_ref";
#TIMESPEC "TS_clk" =PERIOD: "clk_ref": 20ns:PRIORITY 1; #HIGH 50 %;            
# 50MHz

3) The master UCF for the Nexys 2 1200 is on the resource center and also attached below along with the clock portion of the UCF text below.

## Clock pin for Nexys 2 Board
#NET "clk"         LOC = "B8";      # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK,                  Sch name = GCLK0
#NET "clk1"        LOC = "U9";      # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK,         Sch name = GCLK1

 

best regards,

 

Jon

Nexys2_1200General.ucf

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Hi Jon!

I figured out the issue,please find attached clocking wizard selections.The issue is using the CLKFX output .I changed the output pin of DCM to CLK2X(which is used to only double the input frequency 100Mhz) and my design works fine.

But the requirement is to generate 200Mhz clock using the CLKFX pin and google suggests to use rest and locked pins in our design while using CLKFX.

coming back to the clock constraints you asked for 

I am using the system clock 50MHZ which is NET "clk"         LOC = "B8";      # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK,                  Sch name = GCLK0

DCM_CoreGen_Parameters_Screenshot.docx

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Hi @Anusha Kodimela,

I don't see any reason you will not be able to use one of the BTN's(buttons) for the reset and an LED for the Locked signal. I did not see anything specific on the xapp462 linked above.

best regards,

Jon

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