I have used a DCM Core gen to convert the system clock 50MHz to 200 Mhz and added the component to my design,port mapped signals as below not used locked and rest pins while generating the coregen..
the clk signal (output from dcm)is being used now in my design instead of Clock(50 Mhz.I am displaying a count value on a seven segment display which has worked before using dcm (for 50 Mhz clock).I have not seen any error or warnings after implementing the DCM .The simulation seems working as expected.But I am not seeing the output which I have to see in the board after programming it.
Did I forget implementing any other step?My ucf looks like below and If I insert the first lines of the ucf I am getting a timing constraint waning for dcm constraints file.Kindly help.
Question
Anusha Kodimela
Board:Nexys2 Spartan 3E
I have used a DCM Core gen to convert the system clock 50MHz to 200 Mhz and added the component to my design,port mapped signals as below not used locked and rest pins while generating the coregen..
CLKIN_IN => Clock, ----input 50 Mhz clock
CLKFX_OUT => clk,---output 200Mhz clock
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
the clk signal (output from dcm)is being used now in my design instead of Clock(50 Mhz.I am displaying a count value on a seven segment display which has worked before using dcm (for 50 Mhz clock).I have not seen any error or warnings after implementing the DCM .The simulation seems working as expected.But I am not seeing the output which I have to see in the board after programming it.
Did I forget implementing any other step?My ucf looks like below and If I insert the first lines of the ucf I am getting a timing constraint waning for dcm constraints file.Kindly help.
# Clock
#NET "Clock" TNM_NET = "clk_ref";
#TIMESPEC "TS_clk" =PERIOD: "clk_ref": 20ns:PRIORITY 1; #HIGH 50 %;
# 50MHz
NET "Clock" LOC="B8" | IOSTANDARD="LVCMOS33";#50MHz Clock Input
NET "Counter_enable" LOC="L15" | IOSTANDARD="LVCMOS33";#L15-JA1
NET "Counter_disable" LOC="K12" | IOSTANDARD="LVCMOS33";#K12-JA2
NET "Anode_Activate<0>" LOC="F17" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<1>" LOC="H17" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<2>" LOC="C18" | IOSTANDARD="LVCMOS33";
NET "Anode_Activate<3>" LOC="F15" | IOSTANDARD="LVCMOS33";
NET "LED_out<6>" LOC="L18" | IOSTANDARD="LVCMOS33";
NET "LED_out<5>" LOC="F18" | IOSTANDARD="LVCMOS33";
NET "LED_out<4>" LOC="D17" | IOSTANDARD="LVCMOS33";
NET "LED_out<3>" LOC="D16" | IOSTANDARD="LVCMOS33";
NET "LED_out<2>" LOC="G14" | IOSTANDARD="LVCMOS33";
NET "LED_out<1>" LOC="J17" | IOSTANDARD="LVCMOS33";
NET "LED_out<0>" LOC="H14" | IOSTANDARD="LVCMOS33";
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