FIR IP Core Parameters

[alisher_263]

I am designing LPF using FIR IP Core in receiver of Radio.
My sampling frequency is 0.96M Hz and cutoff is 4K. I designed the FIR filter using Matlab and used the coefficients in vivado, FIR IP Core.
My question is whats the relation between sampling frequency and clock frequency for single rate FIR filter? 
For 0.96 as sapling frequency and clock frequency my output signal is not getting filtered as shown in second pic. (Carry_d is input where op_dmod is filter output)
If i increase the clock frequency to 09.6M (with input sampling 0.96M) the output is a clean sine wave but some samples are missed.

 

 

 

[xc6lx45]

Hi,

>> My question is whats the relation between sampling frequency and clock frequency for single rate FIR filter? 

you can demonstrate this if you open the "implementation details" tab on the left and the "channel specification tab" on the right.

For example, I have entered 168 coefficients as an arbitrary, not too small example. Let's assume the FPGA can implement this at 300 MHz, so put 300 into clock frequency (default value).

If the filter needs to process one sample per clock cycle (300 MSPS input rate), I get 84 DSP slices and 0 BRAMs on the "implementation" tab (the design keeps its coefficients in the logic fabric, internally).

On the other hand, if I allow 300 clock cycles / input (1 MHz input sampling frequency), hardware utilization goes down to a single DSP slice and one BRAM. (because internally, it becomes a state machine that reads its coefficient vector from RAM).