I am facing another difficulty with Arty-Z7-20. One of the custom IP´s that I made has only one output (square wave).
I change the output to Output <= ´0´ in the vhdl file using the"Edit IP in Packager" option
Then I re-generate bitstream in the main project after updating the IP.
The resulting bitstream seems to be picking the IP vhdl from somewhere else, because in the resulting design, the square wave signal is still present. (The IP packager shows the correct path to the file, though...)
It seems that the vhdl for the IPs come from somewhere else. No matter what I change in them, the result remains the same ... Go figure ...
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Antonio Fasano
Hi, Guys
I am facing another difficulty with Arty-Z7-20. One of the custom IP´s that I made has only one output (square wave).
I change the output to Output <= ´0´ in the vhdl file using the"Edit IP in Packager" option
Then I re-generate bitstream in the main project after updating the IP.
The resulting bitstream seems to be picking the IP vhdl from somewhere else, because in the resulting design, the square wave signal is still present. (The IP packager shows the correct path to the file, though...)
It seems that the vhdl for the IPs come from somewhere else. No matter what I change in them, the result remains the same ... Go figure ...
Have you ever seen that behaviour ?
Antonio
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