[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair

[aadgl]

(A) Using Vivado 2018 with Arty A7-100.  I have tried many configurations, this is the simplest to duplicate:
> Create project
> Create block diagram
> Add Microblaze
> Add Board SDRAM
> Let Vivado select and connect everything

(B) Generate BitStream produces this error:

[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_i_IBUF] >

    sys_clk_i_IBUF_inst (IBUF.O) is provisionally placed by clockplacer on IOB_X0Y94
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X1Y1

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKFBOUT) is locked to MMCME2_ADV_X1Y1
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

    Clock Rule: rule_bufh_bufr_ramb
    Status: PASS
    Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
    than the capacity of the region
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y19

    Clock Rule: rule_bufhce_mmcm
    Status: PASS
    Rule Description: A BUFH driving an MMCM must both be in the same clock region
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y19
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X1Y1

    Clock Rule: rule_pll_bufhce
    Status: PASS
    Rule Description: A PLL driving a BUFH must both be in the same horizontal row (clockregion-wise)
     design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKOUT3) is locked to PLLE2_ADV_X1Y1
     and design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y19

(C) I have tried adding the < set_property ...>.  Compiling that creates a similar error with a different < set_property ...> ... no apparent workable solution.

If helpful, I can detail other attempts the didn't work.  Is the a procedure for getting SDRAM to work with MicroBlaze in 2018.3?

Thanks,
Dave

[xc6lx45]

Hi,

two ideas (can't tell you the root cause right away, maybe someone else has a better idea):

- The wizard-generated PLL comes with its own input buffer. This can be a problem when I try to drive more than one PLL from the same input pin.

- Are you using any constraint locking the MIG PLL to PLLE2_ADV_X1Y1? A full text search through the project (my own tool would be "grep" in an MSYS command window) should locate it.

[aadgl]

Thanks for the reply.  I am using the Digilent provided board files (including mig.prj) with Vivado 2018.3  For a non-SDRAM configuration, I did have to invert the Reset signal, so maybe there are other misconfigurations in the "out of the box" files.

[aadgl]

Also I noticed the Arty A7 100 documentation:
> https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual?_ga=2.248098821.343193465.1554335188-1186876776.1554335188
In the second to the last paragraph of section 5.1 (DD3RL)
"It is included in the “MIG Project” design resource download. This download also includes a .prj file that can be imported into the wizard to automatically configure it with the options found in Table 2."

> Where is the "MIG Project"?

[jpeyron]

Hi @aadgl,

Welcome to the digilent forums!

Here is a no-verified completed vivado 2018.3 Arty-A7-100 uart/gpio project.  Below are screen shots of the uart/gpio project.

Can you please attach a screen shot of your block design and xdc.

best regard,

Jon

 

[aadgl]

The ZIP downloads and compiles with no errors, thanks  There was a TBD problems with SDK for later.

I noticed the mig.prj in the ZIP is:
>   <Version>4.2</Version>

The one I downloaded is:
> https://reference.digilentinc.com/reference/software/vivado/board-files#installation
> https://github.com/Digilent/vivado-boards/archive/master.zip?_ga=2.26425597.1931504857.1554922614-1469208493.1554922614
>   <Version>2.3</Version>

Where would I get board files that includes mig.prj/4.2c and other (newer) files?

Thanks,
Dave
 

[jpeyron]

Hi @aadgl,

Glad that the downloaded project works for you. thank you for sharing. The board files were downloaded from the Digilent board files here.

best regards,

Jon

[aadgl]

Thanks I am still not finding the mig.prj, version 4.2 that is in the ZIP file.

From that link I went to:
> new/board_files
> arty-a7-100/E.0
That mig.prj file isn't the v4.2:
> <Version>2.3</Version>

 

[aadgl]

Hi Jon,

Thanks again for the example and screen shots.  I haven't resolved the v4.2 vs v2.3 in mig.prj, but was able to create a usable design with E.0 board files and the information you sent:
> Configure clk_wiz:
   - Two outputs (clk_out1 and clk_out2)
   - 166.667 and 200.000 MHz frequencies
   - Invert reset to active low (need to scroll down on that config page)
> Drive mig_7series with the clk_wiz clocks (had to delete clocks Vivado added)
> Configure MicroBlaze to use 83MHz clock from mig_7series

Thanks,
Dave

[jpeyron]

Hi @aadgl,

Can you attach a path to the mig.prj/4.2c ? 

Glad to hear that you are able to create a usable design using this process

- Two outputs (clk_out1 and clk_out2)
   - 166.667 and 200.000 MHz frequencies
   - Invert reset to active low (need to scroll down on that config page)
> Drive mig_7series with the clk_wiz clocks (had to delete clocks Vivado added)
> Configure MicroBlaze to use 83MHz clock from mig_7series

Thank you for sharing what you did.

best regards,

Jon

[aadgl]

Hi Jon,

File is attached and at this location in project:
> Arty_A7_100\Arty_A7_100.srcs\sources_1\bd\design_1\ip\design_1_mig_7series_0_0\design_1_mig_7series_ 0_0\mig.prj

It is v4.2, the v4.2c was a typo.

Dave

mig.prj

[jpeyron]

Hi @aadgl,

I am able to see the difference in the versions between the board files and the Arty-A7 100 project.  I believe the v4.2 is the current MIG 7 version as shown in this user guide.  Its my understanding that vivado typically updates the IP cores like the MIG7 when adding the mig7 to the block design.  

thank you,

Jon