Interface to transfer data from FPGA TO PC Digilent Genesys2 Kintex7 Board

[Anusha Kodimela]

Hello Team!

I am using Genesys2 FPGA for building a module with generates 32 bit values which are to be sent to PC for further analysis and computations.right now I am storing those values in async block ram fifo.

which interface would be good for my requirement to implement as the board that I am using right now Genesys2 Kintex-7 contains both USB-UART and Ethernet(attaching the data sheet) .

could anyone elaborate in brief what steps are to be implemented depending on the interface being used?

Thanks and Regards

Anusha Kodimela

genesys2_rm.pdf

[Anusha Kodimela]

I am running with another issue with DCM and created a new thread for it..Could you please have a look 

 

[jpeyron]

Hi @Anusha Kodimela,

You can design a converter in your hdl which takes in binary 8 bit value from the FIFO and converts it to ascii hex before transmitting to the PC using the USB UART bridge. The other option is once you have transmitted the data to the pc you can use a program to convert the 8 bit data to ascii hex and then read it on the terminal.

best regards,

Jon  

[Anusha Kodimela]

But Jon,

I am expecting the ascii value will be displayed on the terminal(by default) instead of the binary data on the terminal and later we need to decode that ascii code to find the exact data isn't it right?should we assign design a converter in our hdl which takes in binary 8 bit value converts it to ascii hex?

[jpeyron]

Hi @Anusha Kodimela,

I talked with one a more experienced co-worker about your thread.

Looking at the HDL and the attached simulations they think that the data coming out of the FIFO needs to be encoded into asci hex before transmitting the data to the PC or use some kind of program on the PC side to convert the data to asci hex before reading the data in a serial terminal emulator. 

best regards,

Jon

[Anusha Kodimela]

The FIFO generator is the same for ISE and Vivado,its the IP core being used.It is not just specific for ISE.

Are there any experts to whom this thread can be assigned for help?

[jpeyron]

Hi @Anusha Kodimela,

I only used Verilog and VHDL with ISE so I do not have any experience with the settings for the FIFO. I did find a FIFO gen tutorial here. I would also suggest looking through the LogiCORE IP FIFO Generator v9.3 Product Guide as well. Here is the Xilinx FIFO Generator web site.

best regards,

Jon

[Anusha Kodimela]

Hi Jon!

Do you have anything to suggest regarding the FIFO generator,can I directly send the FIFO output bus data(dout) through USB UART bridge?

[Anusha Kodimela]

Hi Jon!

After a count value is generated and written into the FIFO,the value is then being transmitted through the UART bridge.Do you think it is possible to transmit that way as the FIFO gets appended with new value as it gets ?I am thinking this might be the reason for seeing garbage values even after setting the baud correctly (Tx and Rx end).I am using a FIFO with Block Ram with following settings(attached) in the core generator.

Let me know if you have an inputs/advice.

FIF0_Coregen_Screenshots.docx

[Anusha Kodimela]

Hi Jon,The couter and the FIFO coregen is already been tested verified.The only thing I wanted to test was if my tera term is set at 115200(8,N,1) I wanted to modify the same in my desig as well with baud rate of 115200 and parity signal set to 0 so that the Tx(HDL) and Teraterm(Rx) have the same config.I will keep you posted if there is any update

[jpeyron]

Hi @Anusha Kodimela,

I am not seeing anything directly wrong with your HDL. At this point I typically split up the project and verify each individual part I.E.  UART  controller and counter.

best regards,

Jon

[jpeyron]

Hi @Anusha Kodimela,

Please your attach your HDL/UCF files.

best regards,

Jon

[Anusha Kodimela]

Hello Jon!

I have already referred that article before building my UART controller.

I have my count value given to LEDs at the same time reading those values on to the terminal,but for some reason the terminal output shows random charters list!I am unable to decode..As per the atasheet for Genesys 2 Kintex 7 I have set the baud rate as 115200(8,N,1).Attached screenshot below

 

[jpeyron]

Hi @Anusha Kodimela,

Here is a Verilog HDL usb uart bridge/usb host keyboard demo that uses the usb uart which illustrates using the usb uart pins Y23 and Y20 as well as the usb host pins AD23 AE20.

best regard,

Jon 

[Anusha Kodimela]

Hi Jon!

I have two questions regarding USB-UART controller in Genesys2 Kintex7

1.If I use a negative reset input  reset_n    :    IN        STD_LOGIC:= '1'; in my design and that reset input is given to one of the button on the board would it work because all I know is the buttons are usually of value '0' and would be set to '1' only when they are pressed.In my case how would I configure(user constraints file) them If i need a negative reset?

2.The connections for USB-UART is one micro usb for JTAG(J17) to PC for programming and  one micro usb for UART (J15)to PC for communication through tx pin and it requires a Teraterm terminal to view the data that is communicated?

NET "tx" LOC="Y23"|IOSTANDARD="LVCMOS33"; --- this is the transmit pin being used
NET "reset_n" LOC="M19"|IOSTANDARD="LVCMOS33"; -- this is the reset button

Thanks 

Anusha

[jpeyron]

Hi @Anusha Kodimela,

I have responded to your new thread here.

best regards,

Jon

[jpeyron]

Hi @Anusha Kodimela,

Glad to hear using a case statement to assign the bits fixed your issues and thank you for sharing. I did see your hidden post and deleted it after reading it.

best regards,

Jon

[Anusha Kodimela]

Hi jon!

I have resolved that issue using a case statement to assign the bits instead of using the - operator.Hence I have deleted the post also immediately.where you still able to see it?

[jpeyron]

Hi @Anusha Kodimela,

I believe you need to overload the "-" operator like described here.

best regards,

Jon

[Anusha Kodimela]

Hello Jon!

Thank you for giving hope in coding with what ever I am comfortable with.

[jpeyron]

Hi @Anusha Kodimela,

You would be better off using a VHDL/Verilog UART Controller than the AXI UART Lite IP Core. To use this AXI UART lite IP Core without microblaze you would need to facilitate communication with the AXI Bus which is not a trivial task. With a quick google search you should be able to find multiple UART Controllers in either VHDL or Verilog.  

Here is a verilog Genesys 2 keyboard project that uses the usb uart bridge.  Here is the WIKI for the Genesys 2 keyboard demo.

best regards,

Jon

[Anusha Kodimela]

Hi jeypron!

If I had to use my vhdl code in vivado using UART Lite IP core do I still have to use microblaze?I have experience working with IP core when I generated the FIFO Bloc ram and did the port mapping and logic based on the signals used in fifo. Can you guide me with any example which does USB_UART communication not using microblaze as I am not good at creating block design.

[jpeyron]

Hi @Anusha Kodimela,

Here is a Xilinx forum thread discussing Uart IP Core. ISE does not have a UART IP core. EDK does. Since you are using VHDL in ISE you will want to incorporate a UART controller entity to facilitate the uart communication. 

best regards,

Jon

[Anusha Kodimela]

Thanks jpeyron!

I have already built my vhdl code for generating the 32 bit value and then storing it to block ram FIFO. Hence I would continue using the same for my UART USB bridge as well.

But I couldn't find AXI UART Lite v2.0 LogiCORE IP .I am using Xilinx ISE 14.7 DESIGN suite.we have all valid licenses for IP cores.Do you have any idea?

[jpeyron]

Hi @Anusha Kodimela,

You should be able to access the data in the block ram fifo and transfer it to the PC using the usb uart bridge. Here is the getting started with microblaze tutorial that sends data through the usb uart bridge using Microblaze and the uart lite IP Core. Here is the AXI UART Lite v2.0 LogiCORE IP Product Guide.

You can also use HDL(Verliog/VHDL) to do this if you are not using a microblaze design. 

The uart pins are available on the master xdc for the genesys 2 here.

Make sure you are using the digilent board files for either ethernet or usb uart. Here is a tutorial on installing the Digilent board files. 

best regards,

Jon

[Anusha Kodimela]

Thankyou jpeyron!

Could you also elaborate the process for data transfer to PC using USB-UART? I have not seen any IP cores for establishing data transfer from Genesys2 to PC using USB UART .Is the block RAM fifo IP core generated in my design can be accessed from external world(PC) using the USB-UART bridge?

The data sheet for Genesys2 says FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the "Virtual Com Port" or VCP heading,convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins.