I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock .

Following steps i had implemented .

- For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly.

- I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core.

For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine

s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] )

s_axis_data_tlast (I provide this signal from a counter which run upto FFT points)

## Question

## FR 0

I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock .

Following steps i had implemented .

- For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly.

- I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core.

For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine

s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] )

s_axis_data_tlast (I provide this signal from a counter which run upto FFT points)

s_axis_data_tready [ output]

s_axis_data_tvalid [coming from fifo]

s_axis_config_tdata [ passed 0]

s_axis_config_tready [ output]

s_axis_config_tvalid [constant 1]

m_axis_status_tready [constant 1]

m_axis_data_tready [constant 1]

Edited by FRexplanation

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