I’m a little confused about the I/O direction of the USB-UART bridge on the Arty A7 35.
The following is how I think its rigged, does this look right to you guys?
The uart_rxd_out (port name in the xdc): This is data received by the UART from the USB side of the bridge, so it’s an output from the UART side of the bridge and an input to the FPGA.
The uart_txd_in ( port name in the xdc): This is data transmitted by the UART over the bridge to the USB, so its an input on the UART side of the bridge and an output from the FPGA.
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Gra
I’m a little confused about the I/O direction of the USB-UART bridge on the Arty A7 35.
The following is how I think its rigged, does this look right to you guys?
The uart_rxd_out (port name in the xdc): This is data received by the UART from the USB side of the bridge, so it’s an output from the UART side of the bridge and an input to the FPGA.
The uart_txd_in ( port name in the xdc): This is data transmitted by the UART over the bridge to the USB, so its an input on the UART side of the bridge and an output from the FPGA.
Or do I have it the wrong way around?
Thanks for your help Gra
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