"port type is not recognized. " error in vivado

[askhunter]

I'm trying to add module to the schematic I designed, but I got an error because of types.vhdl.

I hope we can solve the problem.
 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package types is

subtype pixel8 is std_logic_vector(7 downto 0); 

type frame_type is array(natural range <>) of pixel8

subtype frame9 is frame_type(0 to 8);

end types;

[zygot]

2 hours ago, askhunter said:

type frame_type is array(natural range <>) of pixel8

Using unconstrained arrays is generally a bad idea for synthesis. Even when you expect to constrain it later when using frame_type don't assume that your synthesis tool will close the loop. Refer to UG901 for Vivado VHDL support and coding guidelines. 

There are differences between synthesis tools from various vendors in how and the order of when code is evaluated.

[askhunter]

I did the "port mapping" manually. then I synthesized and gave no error. 

Does this mean that the "user defined" type , which i defined, will runs on the card without any problems?