Alonso

Can not simulate SRAM to DDR component

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Hello.

I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and  i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. 

Here is a screencapture about simulation. What am i doing wrong?

Thank you.

image.thumb.png.de91d1aa0145e18805144fa014043148.png

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Hi @alonzo,

Welcome to the Digilent Forums!

Are you assigning initial values I.E. 0 or 1 for the signals that are interacting with the project? 

Here is a project that i believe uses the  SRAM to DDR component for the Nexys 4 DDR. Here is the reference manual for the  SRAM to DDR component.

best regards,

Jon

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Hi @Alonso,

Here is a forum thread that deals with simulation of the SRAM to DDR component. Is there a specific issue with the SRAM to DDR component you are concerned about?

best regards,

Jon

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