Alonso

Can not simulate SRAM to DDR component

Recommended Posts

Hello.

I'm trying to simulate SRAM to DDR component from Nexys 4 DDR, I'm using Vivado 2017.2 and  i want to write on DDR. I have respected timming about all entrande signals (RAM) but i never write on DDR, I always see 'ZZZZ' at ddr2_dq signal. 

Here is a screencapture about simulation. What am i doing wrong?

Thank you.

image.thumb.png.de91d1aa0145e18805144fa014043148.png

Share this post


Link to post
Share on other sites

Hi @alonzo,

Welcome to the Digilent Forums!

Are you assigning initial values I.E. 0 or 1 for the signals that are interacting with the project? 

Here is a project that i believe uses the  SRAM to DDR component for the Nexys 4 DDR. Here is the reference manual for the  SRAM to DDR component.

best regards,

Jon

Share this post


Link to post
Share on other sites

Hi @Alonso,

Here is a forum thread that deals with simulation of the SRAM to DDR component. Is there a specific issue with the SRAM to DDR component you are concerned about?

best regards,

Jon

Share this post


Link to post
Share on other sites

I dont know what happend, but i cant simulate it. Can it be simulate?? or have i to use FPGA?

thank you

 

Share this post


Link to post
Share on other sites

Thank you for your answers.

Look that, i simulate the "music looper" project which you told me. And i see that the state (nstate) of SRAM to DDR component never change:

image.thumb.png.f6c855906f13e872eb16efa1525e82b9.png

And the  signal calib_complete, always is X.

Thank you.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now