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Joel Richard

Simulator/emulator for Basys 3?

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Hi,

I am working on some relatively simple programs for a Basys 3. I have to use Verilog and Vivado for this, which is just painfully slow (generate bitstream). Therefore, I am wondering if there is an emulator / simulator for this FGPA board which supports Verilog. It would have to allow me to interact with the device. E.g. I would have to be able to push the buttons, see the LEDs and so on. Exact timing is less of a concern.

Alternatively, are there any tricks to speed up the synthesis (in Vivado or another free program)?

If it is of relevance, this is the configuration I use for my project:

Default Part: xc7a35tcpg236-1
Product: Artix-7

- Joel

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Hi @Joel Richard,

The fastest way of verifying your Verilog code is by using Test-Benches. Furthermore, if you want to do a live capture of your design you can go with ILA. If you want to speed-up  your synthesis, you can increase the number of jobs used by Vivado. The Number of jobs is proportional to the number of local processors to use when launching multiple runs simultaneously.

Best Regards,

Bogdan Vanca   

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I'm going to disagree.  The fastest way to verify your code is working is with formal verification.  Unlike your traditional test bench methodologies, the formal tools tend to be more thorough in finding bugs.  They can often be much faster as well.

functional-v-formal.png

Similarly, generating and running a simulation tends to be much faster when using Verilator over and above what Vivado offers.  As for simulating LEDs and buttons, I cover those in my tutorial.  If you want VGA, I've posted a VGA simulator on line--the same one I used for my BASYS3 board, so it should work for you.  Similarly, I've also posted simulators for the PS/2 mouse and the Flash device, so you should be able to do just about anything with simulation before touching the hardware.  (No, I haven't simulated the PS/2 keyboard--I had to leave something left for you to work on :D )

Dan

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I've got nothing against using an automated tool to do formal verification. For many environments it's a necessity. I'm going to suggest however that you learn how to use the 'classic' simulator tools first. This would be the one that comes with Vivado or ModelSim for Quartus. For those learning the nuances of logic design with an FPGA the old 'use your brain' approach has some advantages.

I'll offer the analogy of flying a commercial airliner as an example. Flying a plane that 99% of the time is so automated that it doesn't need a pilot is easier than flying a single engine prop plane with a stick control. The reason why you need to have hundreds of hours of experience flying planes that are cruder than a 747 or fighter jet before you are allowed to fly one is for that other 1 percent of the flying experience. In the case of a plane you need to be able to know what to do, calmly and in a controlled manner, when flight conditions are beyond the capabilities of the automated systems; or heavens forbid when the automated systems are failing and doing something that imperils of the craft.

In the case of logic simulation it is very instructive and important for development that you gain insight into all of the myriad issues and conditions in your design, and there are a lot of them. Trusting in a software approach to 'fix' your design flaws is not so instructive for the beginner. Few, if any, of the designs that you will do as a novice or for your Basys3 board will need formal verification. Training your mind to improve your design methodology and awareness is an essential part of skill development. Designing a test bench is not easy and that in itself is, similar to flying a Cessna at night in storm conditions, is part of progressing with your design skill.

Once your are good enough to do FPGA development where formal verification is a requirement those tools will augment your mental preparation. It is unfortunate that this part of the trade dosn't have as many texts and examples to help those who have to learn it by themselves.

Being able to use formal verification tools is nice but I'd never hire anyone do to commercial FPGA development who first didn't develop the basic skills, awareness, and testbench acumen using mental understanding and thought processes are that part of competent design. You won't get a gig as captain for a major airline based solely on hours of flight-sim experience. If Uber ever owns an airline I'll stop boarding planes for related though less obvious reasons. 

Edited by zygot

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One typical "small project mistake" that makes Vivado painfully slow is lack of constraints or spare registers for asynchronous inputs / outputs, that is, switches and LEDs. See here https://forum.digilentinc.com/topic/9181-vivado-slowness-reality-check/ for a discussion.

For a conventional, non-interactive simulator, iverilog would be my choice, with gtkwave.

 

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On 3/29/2019 at 9:55 AM, Joel Richard said:

I have to use Verilog and Vivado for this, which is just painfully slow

Thanks @xc6lx45for forcing  me to re-read the original post.  Slow is such an objective assessment. Brewing beer is slow if you intend to start drinking now... Some things just take time. I hate waiting as much as anyone else so I just do something else while the tools are doing their job. Usually, I spend the time thinking about what needs to be done next or assessing what has already been designed. What I read into your post is focussed on 'I have to'. Perhaps this is the crux of the problem. Doing something enjoyable and intellectually challenging is a good antidote for being bored waiting. Simulation is not a way to speed up chores. When I have to do chores that I'd rather not do I've figured out ways to make the time less onerous.

By the way; if you ever do this for a living for a company that does a significant amount of FPGA development your simulation will include the analysis and place and route steps. There is behavioral simulation for the logic and there is timing simulation that attempts to verify how your design bitstream will perform.

Edited by zygot

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