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Basys 3 Artix-7 FPGA Trainer Board




I purchased a Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users and I am looking for the phase noise (jitter) graph for the FPGA output clock.



Can you provide that to me?

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Hi @mgooding9,

I have moved your question to a more appropriate section of the Forum.

We (Digilent) do not have a phase noise graph specific to our boards within our own documentation, but you can find details for the 100 MHz oscillator that we use on page 3 of it's datasheet here. If you are looking for the output jitter and duty cycle of the clocks and PLLs within the Artix 7 chip, I would recommend looking at the Artix-7 DC and AC Switching Characteristics datasheet from Xilinx.

Let me know if you have any further questions.


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