mgooding9 Posted March 27, 2019 Share Posted March 27, 2019 Hi, I purchased a Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users and I am looking for the phase noise (jitter) graph for the FPGA output clock. https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ Can you provide that to me? Link to comment Share on other sites More sharing options...
JColvin Posted March 27, 2019 Share Posted March 27, 2019 Hi @mgooding9, I have moved your question to a more appropriate section of the Forum. We (Digilent) do not have a phase noise graph specific to our boards within our own documentation, but you can find details for the 100 MHz oscillator that we use on page 3 of it's datasheet here. If you are looking for the output jitter and duty cycle of the clocks and PLLs within the Artix 7 chip, I would recommend looking at the Artix-7 DC and AC Switching Characteristics datasheet from Xilinx. Let me know if you have any further questions. Thanks, JColvin Link to comment Share on other sites More sharing options...
Question
mgooding9
Hi,
I purchased a Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users and I am looking for the phase noise (jitter) graph for the FPGA output clock.
https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/
Can you provide that to me?
Link to comment
Share on other sites
1 answer to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.