How to read from SPI Flash on Nexys A7 (previously Nexys 4 DDR)

[yildizabdullah]

I need to read from Quad-SPI Flash device on Nexys A7. Reference manual has the following statements:

All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2.

How can I utilize the STARTUPE2 primitive in order to drive SCK pin properly during a read operation?

[jpeyron]

Hi @yildizabdullah,

Here, here,  here and here  are forum threads that should be helpful for your project.

best regards,

Jon

[D@n]

@yildizabdullah,

You might also find these blog articles useful: Here's one on building a basic SPI flash controller, and here's a more detailed one discussing how to build a full-featured  QSPI flash controller.

Dan

[yildizabdullah]

@D@n @jpeyron

Do I have to include a pin constraint for spi_clk in .ucf file? I suppose I have to, but get an error during Implement Design step in Xilinx ISE as 

ERROR:MapLib:30 - LOC constraint E9 on spi_clk is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

[D@n]

@yildizabdullah,

Are you using ISE or Vivado?  I would've expected Vivado if you are working with the Nexys A7.  ISE uses UCF files, Vivado uses XDC files--that's why I'm asking.  Either way, you don't need to declare the SPI SCK pin in the constraints file.  However, getting access to it is a bit more involved.  To get access to the spi_clk pin you need to use a special primitive, either STARTUP_SPARTAN6 for the S6 (not the Nexys A7) or the STARTUPE2.  You can find an example of using the STARTUPE2 primitive to get access to the SPI clock pin here, and more general instructions here.

Dan

[yildizabdullah]

On 4/5/2019 at 6:34 PM, D@n said:

@yildizabdullah,

Are you using ISE or Vivado?  I would've expected Vivado if you are working with the Nexys A7.  ISE uses UCF files, Vivado uses XDC files--that's why I'm asking.  Either way, you don't need to declare the SPI SCK pin in the constraints file.  However, getting access to it is a bit more involved.  To get access to the spi_clk pin you need to use a special primitive, either STARTUP_SPARTAN6 for the S6 (not the Nexys A7) or the STARTUPE2.  You can find an example of using the STARTUPE2 primitive to get access to the SPI clock pin here, and more general instructions here.

Dan

@D@n I work on ISE and possibly I am doing something wrong in my SPI Flash controller. Thanks for your suggestions.

[yildizabdullah]

@jpeyron @D@n I fixed the bug in my SPI Flash controller design. Now I can read from Flash memory.

[jpeyron]

Hi @yildizabdullah,

Glad to hear you have resolved the issue with your spi flash controller. thank you for sharing that its resolved.

best regards,

Jon

PS- on my first verilog spi controller i had one of the signals set as an input instead of inout. It took a little bit to figure that one out.