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wilfredk

Image Processing on ZYBO Zynq-7000 Co-processing System

Question

Hi, 

I am fairly new to the creation of IPs using Vivado HLS. For the current project that I am working on I have been tinkering with a Linux OS that I installed on ZYBO Zynq Z-7010 AP Soc. The board has a very modest resources and compared to other high end boards. I have installed Xillinux an operating system that makes it possible to communicated using device files that are located in /dev/ folder named as xillybus_read_* and xillybus_write_* . I have created an IP using Vivado HLS that would carry a 2D convolution. 

When I run the c_simulation through Vivado hls it gives me the desired output but when I run the same through a program created on the host OS that is supposed to communicate with the PL it does not return a desired output or anywhere near it. 

I am attaching the IP core file, testbench file created in Vivado HLS and the C++ program running on the PS for communicating with the IP.

Thank you in advance.

core.cpp tb_core.cpp coprocessing.cpp

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Digilent has only worked with Petalinux. We suggest contacting Xillybus for this.

Or maybe other forum members have Xillinux experience and they can help out.

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