I'm new to the programming industry and I'm currently working on a student project that aims to implement a frequncy meter in an FPGA card, I'm using nexys 3.
I found a code online as shown below and I tried to follow it exactly with changing the pins, but I keep receiving this error
module counter1(
rst,
clk,
count
);
parameter size = 33;
input rst; // reset the counter
input clk; // connected to WireFrame on board 25Mhz crystal.
output [size-1:0] count;
reg [size-1:0] count=0; // Signals assigned
// within an always
// (or initial)block
// must be of type reg
// The always statement below is a parallel
// execution statement that
// executes any time the signals
// rst or clk transition from low to high
always @ (posedge clk)
begin
if (!rst) // This causes reset of the cntr
count = 0;
else
count = count + 1'b1;
end
endmodule
module counter(rst, clk, count);
// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language
parameter size = 33;
input rst; // These inputs/outputs represent
input clk; // connections to the module.
output [size-1:0] count;
reg [size-1:0] count=0; // Signals assigned
// within an always
// (or initial)block
// must be of type reg
// The always statement below is a parallel
// execution statement that
// executes any time the signals
// rst or clk transition from low to high
always @ (posedge clk or negedge rst )
begin
if (!rst) // This causes reset of the cntr
count = 0;
else if(count<32'hFFFFFFFF)
begin
count = count + 1'b1;
end
end
endmodule
`timescale 1ns/1ps // simmulation happen in picosecond time base ,
// we have up scaled it it to ns
// when we say #5 it will mean 5 ns , and when we say #1000 it will 1000ns, 1us
module counter_testbench();
reg clock_tb,reset;
wire [32:0]out_tb;
counter t0(reset,clock_tb,out_tb); //create an instance of the counter module which is under test
initial
begin
$monitor("%g,out_tb=%d,reset=%b",$time,out_tb,reset); // these values will be visible in the transcript window at the bottom
clock_tb=0;
reset=1; //enable the counter module ,reset is active low input
#100 // right here we should have (200/5)/2 = 20 in the cout output value
reset=0; //reset the timer module for a while
#300
reset=1;
#1000
$stop(); // rigth here we will have (1000/5)2=100 in the count output
end
always #5 clock_tb=~clock_tb; // genrate clock by toggling Clock line ever 5 unit of time
endmodule
`timescale 1ns / 1ps
module freq_meter(
clk,
segment,
digit,
sigin
);
output [7:0]segment;
output [7:0]digit;
input clk;
input sigin;
//reg [7:0]segment=8'b00;
reg [7:0]digit = 8'b01;
reg [31:0]freq;
wire [3:0]dispdata[7:0];
reg [2:0]digit_scan;
reg [23:0]disp_scanner;
reg [31:0]gatecounter;
reg gate;
wire [31:0]count;
bcd_to_seg s1(dispdata[digit_scan],segment);
bin_to_bcd b1(freq,dispdata[0],dispdata[1],dispdata[2],dispdata[3],dispdata[4],dispdata[5],dispdata[6],dispdata[7]);
counter c1(gate,sigin,count);
always @(posedge clk )
begin
if(!gatecounter)
begin
gatecounter = 'd25000000;
gate =0;
freq = count;
end // if !gatecounter end
else
begin
gate =1;
end
gatecounter = gatecounter - 1'b1;
disp_scanner = disp_scanner +1'b1;
if(disp_scanner=='d50000)
begin
digit = {digit[6:0],digit[7]};
digit_scan=digit_scan+'d1;
disp_scanner = 0;
end
end // always end
endmodule
module nec_decoder (
IR,
clk,
address,
data,
dataready
);
parameter CLOCK_INPUT=100000000; // in Hz
parameter OUT_TIME50ms= 1250000; //for 25Mhz input
parameter OUT_TIME200ms= 5000000;
parameter [15:0]TICKS11ms= 11000;
parameter [15:0]TICKS8ms = 8000;
parameter [15:0]TICKS5o5ms = 5500;
parameter [15:0]TICKS3ms = 3000;
parameter [15:0]TICKS1o9ms = 1900;
parameter [15:0]TICKS2o7ms = 2700;
parameter [15:0]TICKS2o3ms = 2300;
parameter [15:0]TICKS1o2ms = 1200;
parameter [15:0]TICKS0o2ms = 200;
input IR;
input clk;
output [7:0]address;
output [7:0]data;
output dataready;
reg dataready=0;
wire [15:0]elapsed_time;
reg [7:0]address=0;
reg [7:0]data=0;
reg [15:0]PREPULSE=TICKS8ms;
reg [15:0]TIMEOUT=TICKS11ms;
reg [31:0]rxbuffer=0;
reg [6:0]necpoj=0;
reg [1:0]cleaer_timer_prescale=0;
reg [23:0]outtimer=0;
reg clear=0;
reg [1:0]last=0;
timer t0(clear,clk,elapsed_time);
always @(posedge clk )
begin
if(clear)
begin
clear=1'b0; // release the timer reset
end
outtimer=outtimer + 1'b1; //this code will maintain the data read pin high for a while after receiving the valid data
if(outtimer==OUT_TIME200ms ) // pin goes low automaically after
begin
dataready=1'b0;
outtimer =OUT_TIME50ms;
end
else if( outtimer==OUT_TIME50ms) // this time is for repeate codes
begin
dataready=1'b1;
end
if( last[0] ^ last[1] )
begin
if ((elapsed_time>PREPULSE) && (elapsed_time<TIMEOUT) )
beginif((necpoj=='d1) || (necpoj=='d2)) //whenwearehearitmeans 9msledingpulsehasendedandnowwearenecpoj=1ornecpoj=2beginif((IR) && (necpoj=='d1))
begin
necpoj=necpoj+1'b1;
TIMEOUT=TICKS5o5ms;//timeoutfor 3rdpulse 5.5msPREPULSE=TICKS1o9ms;//PREPULSEfor 3rdpulse 3msendelseif((!IR)&& (necpoj=='d2))
begin
if((elapsed_time>TICKS1o9ms)&&(elapsed_time<TICKS2o7ms) ) //checkifitisarepeatcodebeginif(dataready)
begindataready=1'b0;
outtimer =0;
end
necpoj=0;
TIMEOUT = TICKS11ms; // yes it is a repeat code so expect new transmission or a repeat code
PREPULSE = TICKS8ms;
end
else
begin
necpoj =necpoj+1'b1;
TIMEOUT=TICKS2o3ms;//nowdatastartssotimeoutis 2.3msPREPULSE=TICKS0o2ms;endendelse//thisblockhandletheconditonifanyerroroccurafterthecompletingtheprepulsesbeginnecpoj=0;//resetthestatemachineTIMEOUT=TICKS11ms;PREPULSE=TICKS8ms;endendelseif(necpoj>'d2 && necpoj< 'd70) //now we are picking the data
begin
necpoj=necpoj+1'b1; //necpoj sill inrement on every edge
if(necpoj[0]) // here we check the if necpoj is an odd number because when necpoj goes greater then 3 then
//necpoj will always be and odd value when a single bit tranmission is over
begin
rxbuffer=rxbuffer<<1; //shift the buffer
if(elapsed_time>TICKS1o2ms) //we are here means we just recevied the edge of finished tranmission of a bit
// so if last edge was more than 1.24 ms then the bit which is just over is one else it is zero
begin
rxbuffer[0] = 1'h1;
end
else
begin
rxbuffer[0] = 1'h0;
end
end
if(necpoj >66) // we have reached (Leading pulse 2 +address 16+~address16+ command 16+ ~command 16+ last final burst first edge 1)=67th edge of the message frame means the date tranmission is now over
begin
if((!(rxbuffer[31:24] & rxbuffer[23:16])) & (!(rxbuffer[15:8] & rxbuffer[7:0]))) // check weather the received data is vaild or not
begin
data = rxbuffer[15:8];
address = rxbuffer[31:24];
outtimer =0;
dataready =1;
end
else
begin
data =8'b00;
dataready=0;
end
rxbuffer=0; //clear the buffer
TIMEOUT = TICKS11ms; // weather we received the vaild data or not we have to reset the state machine
PREPULSE = TICKS8ms;
necpoj=0;
end
end
else
begin
necpoj=0;
TIMEOUT = TICKS11ms; // some error occured reset state machine
PREPULSE = TICKS8ms;
end
end
else
begin
if(IR) //we are here means that after a longtimeout or PREPULSE we just detect a pulse which may be the start of 9ms pulse
necpoj = 0; // no it's not start of 9ms pulse
else
necpoj = 'd1; // yes it could be the start of 9ms pulse
TIMEOUT = TICKS11ms; //default timing
PREPULSE = TICKS8ms;
end
cleaer_timer_prescale=0;
clear=1'b1;
//clear the timer
end
last= {last[0],IR};
end
endmodule
library verilog;
use verilog.vl_types.all;
entity counter is
generic(
size : integer := 33
);
port(
rst : in vl_logic;
clk : in vl_logic;
count : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of size : constant is 1;
end counter;
and the error :
ERROR:MapLib:30 - LOC constraint LL8 on sigin is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
thank you for kindly understant that I don't come for an electrnic background or anything related.
Question
destinyh
Hello everyone ?
I'm new to the programming industry and I'm currently working on a student project that aims to implement a frequncy meter in an FPGA card, I'm using nexys 3.
I found a code online as shown below and I tried to follow it exactly with changing the pins, but I keep receiving this error
the code is below :
module bcd_to_seg ( bcd, segment ); output [6:0]segment; input [3:0]bcd; reg [6:0]segment; always @(bcd) begin case(bcd) 4'b0000:begin //0 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b0; //g end 4'b0001:begin //1 segment[0] = 1'b0; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b0; //d segment[4] = 1'b0; //e segment[5] = 1'b0; //f segment[6] = 1'b0; //g end 4'b0010:begin //2 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b0; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b0; //f segment[6] = 1'b1; //g end 4'b0011:begin //3 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b0; //e segment[5] = 1'b0; //f segment[6] = 1'b1; //g end 4'b0100:begin //4 segment[0] = 1'b0; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b0; //d segment[4] = 1'b0; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b0101:begin //5 segment[0] = 1'b1; //a segment[1] = 1'b0; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b0; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b0110:begin //6 segment[0] = 1'b1; //a segment[1] = 1'b0; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b0111:begin //7 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b0; //d segment[4] = 1'b0; //e segment[5] = 1'b0; //f segment[6] = 1'b0; //g end 4'b1000:begin //8 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b1001:begin //9 segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b0; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b1010:begin //A segment[0] = 1'b1; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b0; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b1011:begin //B segment[0] = 1'b0; //a segment[1] = 1'b0; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b1100:begin //C segment[0] = 1'b1; //a segment[1] = 1'b0; //b segment[2] = 1'b0; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b0; //g end 4'b1101:begin //D segment[0] = 1'b0; //a segment[1] = 1'b1; //b segment[2] = 1'b1; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b0; //f segment[6] = 1'b1; //g end 4'b1110:begin //E segment[0] = 1'b1; //a segment[1] = 1'b0; //b segment[2] = 1'b0; //c segment[3] = 1'b1; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end 4'b1111:begin //F segment[0] = 1'b1; //a segment[1] = 1'b0; //b segment[2] = 1'b0; //c segment[3] = 1'b0; //d segment[4] = 1'b1; //e segment[5] = 1'b1; //f segment[6] = 1'b1; //g end endcase end //assign segment[0]= ((!bcd[0]) && (!bcd[2])) || (bcd[0] && bcd[2]) || bcd[1] || bcd[3]; //assign segment[1]= (!bcd[2]) || (bcd[0] && bcd[1]) || ((!bcd[0]) && (!bcd[1])); //assign segment[2]= (bcd[0]) || (!bcd[1]) || (bcd[2]); //assign segment[3]= ((!bcd[0]) && (!bcd[2])) || ((bcd[1]) && (!bcd[2])) || (bcd[3]) || ((!bcd[0]) && (bcd[1])) || ((bcd[0]) && (!bcd[1]) && (bcd[2])); //assign segment[4]= ((!bcd[0]) && (!bcd[2])) || ((!bcd[0]) && (bcd[1])); //assign segment[5]= (bcd[3])||((!bcd[0]) && (bcd[2])) || ((!bcd[0]) && (!bcd[1])) ||((!bcd[1]) && (bcd[2])) ; //assign segment[6]= ((!bcd[0]) && (bcd[2])) || ((!bcd[1]) && (bcd[2])) || (bcd[3]) || ((bcd[1]) && (!bcd[2])) ; /* f(a) = !A!C + AC + B + D f(b) = !C + AB + !A!B f(c) = A + !B + C f(d) = !A!C + B!C + D + !AB + A!BC f(e) = !A!C + !AB f(f) = D +!AC + !A!B + !BC f(g) = !AC + !BC + D + B!C */ endmodule
module bin_to_bcd(bin,ONES,TENS,HUNDREDS,TH,TENTH,HUNTH,MIL,TENMIL); parameter BIN_N_bits=24; input [26:0] bin; output [3:0] ONES, TENS ,HUNDREDS ,TH,TENTH,HUNTH,MIL,TENMIL; reg [3:0] ONES, TENS ,HUNDREDS ,TH,TENTH,HUNTH,MIL,TENMIL,HUNDMIL; integer i; always @(bin) begin ONES=0; TENS=0; HUNDREDS=0; TH=0; TENTH=0; HUNTH=0; MIL=0; TENMIL=0; for(i=26;i>=0;i=i-1) //26 bit binary value begin if(HUNDMIL>=5) HUNDMIL =HUNDMIL +3; if(TENMIL>=5) TENMIL = TENMIL +3; if(MIL>=5) MIL=MIL+3; if(HUNTH>=5) HUNTH=HUNTH+3; if(TENTH>=5) TENTH=TENTH+3; if(TH>=5) TH=TH+3; if(HUNDREDS>=5) HUNDREDS=HUNDREDS+3; if(TENS>=5) TENS=TENS+3; if(ONES>=5) ONES =ONES+3; HUNDMIL = HUNDMIL <<1; HUNDMIL[0] =TENMIL[3]; TENMIL = TENMIL <<1; TENMIL[0] = MIL[3]; MIL = MIL <<1; MIL[0] = HUNTH[3]; HUNTH = HUNTH <<1; HUNTH[0] = TENTH[3]; TENTH = TENTH<<1; TENTH[0] = TH[3]; TH= TH <<1; TH[0]= HUNDREDS [3]; HUNDREDS = HUNDREDS<<1; HUNDREDS[0] = TENS[3]; TENS = TENS <<1; TENS[0] = ONES[3]; ONES = ONES <<1; ONES[0] = bin[i]; end //for loop end end//always end endmodule
module counter1( rst, clk, count ); parameter size = 33; input rst; // reset the counter input clk; // connected to WireFrame on board 25Mhz crystal. output [size-1:0] count; reg [size-1:0] count=0; // Signals assigned // within an always // (or initial)block // must be of type reg // The always statement below is a parallel // execution statement that // executes any time the signals // rst or clk transition from low to high always @ (posedge clk) begin if (!rst) // This causes reset of the cntr count = 0; else count = count + 1'b1; end endmodule
module counter(rst, clk, count); // TITLE 'Divide-by-20 Counter with enables' // enable CEP is a clock enable only // enable CET is a clock enable and // enables the TC output // a counter using the Verilog language parameter size = 33; input rst; // These inputs/outputs represent input clk; // connections to the module. output [size-1:0] count; reg [size-1:0] count=0; // Signals assigned // within an always // (or initial)block // must be of type reg // The always statement below is a parallel // execution statement that // executes any time the signals // rst or clk transition from low to high always @ (posedge clk or negedge rst ) begin if (!rst) // This causes reset of the cntr count = 0; else if(count<32'hFFFFFFFF) begin count = count + 1'b1; end end endmodule
`timescale 1ns/1ps // simmulation happen in picosecond time base , // we have up scaled it it to ns // when we say #5 it will mean 5 ns , and when we say #1000 it will 1000ns, 1us module counter_testbench(); reg clock_tb,reset; wire [32:0]out_tb; counter t0(reset,clock_tb,out_tb); //create an instance of the counter module which is under test initial begin $monitor("%g,out_tb=%d,reset=%b",$time,out_tb,reset); // these values will be visible in the transcript window at the bottom clock_tb=0; reset=1; //enable the counter module ,reset is active low input #100 // right here we should have (200/5)/2 = 20 in the cout output value reset=0; //reset the timer module for a while #300 reset=1; #1000 $stop(); // rigth here we will have (1000/5)2=100 in the count output end always #5 clock_tb=~clock_tb; // genrate clock by toggling Clock line ever 5 unit of time endmodule
`timescale 1ns / 1ps module freq_meter( clk, segment, digit, sigin ); output [7:0]segment; output [7:0]digit; input clk; input sigin; //reg [7:0]segment=8'b00; reg [7:0]digit = 8'b01; reg [31:0]freq; wire [3:0]dispdata[7:0]; reg [2:0]digit_scan; reg [23:0]disp_scanner; reg [31:0]gatecounter; reg gate; wire [31:0]count; bcd_to_seg s1(dispdata[digit_scan],segment); bin_to_bcd b1(freq,dispdata[0],dispdata[1],dispdata[2],dispdata[3],dispdata[4],dispdata[5],dispdata[6],dispdata[7]); counter c1(gate,sigin,count); always @(posedge clk ) begin if(!gatecounter) begin gatecounter = 'd25000000; gate =0; freq = count; end // if !gatecounter end else begin gate =1; end gatecounter = gatecounter - 1'b1; disp_scanner = disp_scanner +1'b1; if(disp_scanner=='d50000) begin digit = {digit[6:0],digit[7]}; digit_scan=digit_scan+'d1; disp_scanner = 0; end end // always end endmodule
library verilog; use verilog.vl_types.all; entity counter is generic( size : integer := 33 ); port( rst : in vl_logic; clk : in vl_logic; count : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of size : constant is 1; end counter;
and the error :
ERROR:MapLib:30 - LOC constraint LL8 on sigin is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
thank you for kindly understant that I don't come for an electrnic background or anything related.
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